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    1.
    发明专利
    未知

    公开(公告)号：DE1234055B

    公开(公告)日：1967-02-09

    申请号：DEJ0026818

    申请日：1964-11-05

    Applicant: IBM DEUTSCHLAND

    Inventor： ABERNATHY ROGER EDWIN ,  GENG ROLAND ,  ONWILER WALTER NEWTON ,  TARANTO ROBERT

    IPC: G06F7/49 ,  G06F7/50

    Abstract: 1,083,838. Digital computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 22, 1965 [Nov. 5, 1964], No. 44751/65. Heading G4A. In an electric digital system for adding or subtracting numbers in a pair of registers R, L, Fig. 2, in which the contents of each is successively incremented or decremented until a carry takes place in one indicating that the result is in the other, the contents of at least one of the registers is initially compared with zero and the radix whereby the registers L, R to be incremented or decremented are chosen in order to obtain a minimum number of steps. The example of Fig. 2 is applied to registers R, L having four binary bits (radix 16), but binary coded decimal system is referred to. The registers R, L form single digit components of multi-order registers (Fig. 3, not shown) and to which the process is applied to each order stage sequentially. The contents of the registers are first tested for zero, thereby stopping further operation and indicating directly, when one operand is zero, that the other register contains the result. The contents, if non-zero, are then compared at V to determine which is nearer to zero or to the radix B as by comparison with B/2, whereby control circuit A-S-ST is set to operate the incrementing, decrementing circuit M to selectively operate on the registers R, L until a carry is indicated in registers UR, UL. In the event of the result being in the register other than that in which it is required, the circuit (M2) (Figs. 3 or 4, not shown) is used to transfer the contents to the required register. In the modification of (Fig. 4, not shown) the contents of only one register (R) is compared with B/2. A detailed circuit (Fig. 9, not shown) illustrates a system for incrementing or decrementing the registers by gating oppositely phased timing pulses (R1), (R3), the operation continuing until a carry is indicated in registers (UR), (UL).

    Data storage apparatus
    3.
    发明专利
    Data storage apparatus 未知

    公开(公告)号：GB1078383A

    公开(公告)日：1967-08-09

    申请号：GB1118966

    申请日：1966-03-15

    Applicant: IBM

    Inventor： SCHELER TITUS ,  GENG ROLAND ,  KUENDEL GERHARD ,  HODGES PAUL ,  UTLEY BRIAN GEORGE

    IPC: G11C21/00

    Abstract: 1,078,383. Data storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 15, 1966 [March 26, 1965], No. 11189/66. Heading G4C. A recirculating store has (n+1) storage positions to enable a set of n characters stored therein to be read in the reverse order, there being means for reading out every n character times from a particular storage position. Referring to Fig. 1 (not shown), a delay line (LSp) has outputs (N, L) n and (n+ 1) character positions from the input (E), either being connectible to feed the input (E) for recirculation. Reversal is achieved by using the (n+1) output (L) for recirculation and gating (U) a character from the n output every n character times, using a counter (ZZ). Leading zeros may be suppressed by changing the output used for recirculation under control of comparison of the two outputs (N, L). A magnetic drum or disc may replace the delay line.

    Apparatus for combining arithmetically two numbers
    6.
    发明专利
    Apparatus for combining arithmetically two numbers 未知

    公开(公告)号：GB1083838A

    公开(公告)日：1967-09-20

    申请号：GB4475165

    申请日：1965-10-22

    Applicant: IBM

    Inventor： ABERNATHY ROGER EDWIN ,  GENG ROLAND ,  ONWILER WALTER NEWTON ,  TARANTO ROBERT

    IPC: G06F7/49

    Abstract: 1,083,838. Digital computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 22, 1965 [Nov. 5, 1964], No. 44751/65. Heading G4A. In an electric digital system for adding or subtracting numbers in a pair of registers R, L, Fig. 2, in which the contents of each is successively incremented or decremented until a carry takes place in one indicating that the result is in the other, the contents of at least one of the registers is initially compared with zero and the radix whereby the registers L, R to be incremented or decremented are chosen in order to obtain a minimum number of steps. The example of Fig. 2 is applied to registers R, L having four binary bits (radix 16), but binary coded decimal system is referred to. The registers R, L form single digit components of multi-order registers (Fig. 3, not shown) and to which the process is applied to each order stage sequentially. The contents of the registers are first tested for zero, thereby stopping further operation and indicating directly, when one operand is zero, that the other register contains the result. The contents, if non-zero, are then compared at V to determine which is nearer to zero or to the radix B as by comparison with B/2, whereby control circuit A-S-ST is set to operate the incrementing, decrementing circuit M to selectively operate on the registers R, L until a carry is indicated in registers UR, UL. In the event of the result being in the register other than that in which it is required, the circuit (M2) (Figs. 3 or 4, not shown) is used to transfer the contents to the required register. In the modification of (Fig. 4, not shown) the contents of only one register (R) is compared with B/2. A detailed circuit (Fig. 9, not shown) illustrates a system for incrementing or decrementing the registers by gating oppositely phased timing pulses (R1), (R3), the operation continuing until a carry is indicated in registers (UR), (UL).

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