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    2.
    发明专利
    未知

    公开(公告)号：FR2406851A1

    公开(公告)日：1979-05-18

    申请号：FR7828926

    申请日：1978-10-02

    Applicant: IBM

    Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

    IPC: G06F9/22 ,  G06F9/16

    Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

    CHECK CIRCUIT FOR SYNCHRONIZED CLOCKS
    5.
    发明专利
    CHECK CIRCUIT FOR SYNCHRONIZED CLOCKS 未知

    公开(公告)号：CA1113575A

    公开(公告)日：1981-12-01

    申请号：CA340653

    申请日：1979-11-26

    Applicant: IBM

    Inventor： BLUM ARNOLD ,  GENG HELLMUTH R ,  SCHULZE-SCHOELLING HERMANN

    IPC: G01R31/28 ,  G01R31/3183 ,  G04D7/00 ,  G06F1/04 ,  H03K5/26 ,  H04M3/22 ,  H04M3/24

    Abstract: CLOCK CHECK CIRCUITS USING DELAYED SIGNALS In a data processing or transmission system which includes at least two synchronized clocks, for example - T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.

    DEVICE FOR ADDRESS TRANSLATION
    6.
    发明专利
    DEVICE FOR ADDRESS TRANSLATION 未知

    公开(公告)号：CA981370A

    公开(公告)日：1976-01-06

    申请号：CA146795

    申请日：1972-07-11

    Applicant: IBM

    Inventor： BOGER KLAUS ,  GENG HELLMUTH R ,  GOETZE VOLKMAR ,  HAJDU JOHANN

    IPC: G06F12/10

    Abstract: In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.

    7.
    发明专利
    未知

    公开(公告)号：FR2406851B1

    公开(公告)日：1986-04-11

    申请号：FR7828926

    申请日：1978-10-02

    Applicant: IBM

    Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

    IPC: G06F9/22

    Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

    8.
    发明专利
    未知

    公开(公告)号：DE2134816A1

    公开(公告)日：1973-02-01

    申请号：DE2134816

    申请日：1971-07-13

    Applicant: IBM DEUTSCHLAND

    Inventor： BOGER KLAUS ,  GOETZE VOLKMAR ,  GENG HELLMUTH R ,  HAJDU JOHANN

    IPC: G06F12/10 ,  G06F13/06

    Abstract: In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.

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