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    1.
    发明专利
    未知

    公开(公告)号：DE3382758D1

    公开(公告)日：1994-11-03

    申请号：DE3382758

    申请日：1983-11-10

    Applicant: IBM

    Inventor： AGNEW PALMER WRIGHT ,  ERHARD JOHN JOSEPH ,  KELLERMAN ANNE SHEILA

    IPC: G06F12/00 ,  G06F17/21 ,  G06F17/22 ,  G06F15/20

    Abstract: A method of transforming a first editable form (42, 24a) of a document prepared by an interactive text processing system (34-42) into a second and incompatible editable form (24b) for use in another interactive or batch text processing system (20-30) through the use of a transform mechanism (48) is described. A significant step of this method requires the identification of a limited number of key state variables, whose values collectively identify the necessary state information for transforming the first document form to the second. After the key state variables have been identified, the actual number of combinations thereof is determined. For each first document form input item encountered by the transform mechanism, and for each combination of key state variables in which that input item can be encountered, one or more output items for the second document form is explicitly defined as the transform thereof. In addition, the state of the transform mechanism after each such transform has occurred, must also be specified. The described method will also resolve the actual state that exists at the start of each document. It is also adapted to handle sub-documents, such as margin text, existing within a document to be transformed.

    3.
    发明专利
    未知

    公开(公告)号：DE69208533T2

    公开(公告)日：1996-11-07

    申请号：DE69208533

    申请日：1992-05-14

    Applicant: IBM

    Inventor： AGNEW PALMER WRIGHT ,  FERGUSON DOUGLAS KERR ,  KELLERMAN ANNE SHEILA ,  KELLERMAN THOMAS BEN

    IPC: G02B6/36 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/16 ,  G06F1/18 ,  G06F3/00 ,  H01R13/72 ,  H02G11/02

    Abstract: An electronic computer including microprocessor means, memory means and Input/Output (I/O) means wherein the I/O means comprises a retractable optical fiber connector assembly (15). The retractable optical fiber connector assembly (15) includes a rotatable spool (17) and a pair of optical fibers (19) for being wound thereabout, these fibers in turn optically connected to optoelectronic means (71) within the computer (as part of the I/O means). On the opposing ends of these optical fibers (19) are desired connectors (37) (e.g., those of the push-pull variety) for being connected to associated opticaltype connectors which in turn may form part of various peripheral equipment (e.g., MODEMS, printers, etc.) or other computers to which this computer may be connected.

    5.
    发明专利
    未知

    公开(公告)号：DE69208533D1

    公开(公告)日：1996-04-04

    申请号：DE69208533

    申请日：1992-05-14

    Applicant: IBM

    Inventor： AGNEW PALMER WRIGHT ,  FERGUSON DOUGLAS KERR ,  KELLERMAN ANNE SHEILA ,  KELLERMAN THOMAS BEN

    IPC: G02B6/36 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/16 ,  G06F1/18 ,  G06F3/00 ,  H01R13/72 ,  H02G11/02

    Abstract: An electronic computer including microprocessor means, memory means and Input/Output (I/O) means wherein the I/O means comprises a retractable optical fiber connector assembly (15). The retractable optical fiber connector assembly (15) includes a rotatable spool (17) and a pair of optical fibers (19) for being wound thereabout, these fibers in turn optically connected to optoelectronic means (71) within the computer (as part of the I/O means). On the opposing ends of these optical fibers (19) are desired connectors (37) (e.g., those of the push-pull variety) for being connected to associated opticaltype connectors which in turn may form part of various peripheral equipment (e.g., MODEMS, printers, etc.) or other computers to which this computer may be connected.

    6.
    发明专利
    未知

    公开(公告)号：DE3382758T2

    公开(公告)日：1995-03-30

    申请号：DE3382758

    申请日：1983-11-10

    Applicant: IBM

    Inventor： AGNEW PALMER WRIGHT ,  ERHARD JOHN JOSEPH ,  KELLERMAN ANNE SHEILA

    IPC: G06F12/00 ,  G06F17/21 ,  G06F17/22

    Abstract: A method of transforming a first editable form (42, 24a) of a document prepared by an interactive text processing system (34-42) into a second and incompatible editable form (24b) for use in another interactive or batch text processing system (20-30) through the use of a transform mechanism (48) is described. A significant step of this method requires the identification of a limited number of key state variables, whose values collectively identify the necessary state information for transforming the first document form to the second. After the key state variables have been identified, the actual number of combinations thereof is determined. For each first document form input item encountered by the transform mechanism, and for each combination of key state variables in which that input item can be encountered, one or more output items for the second document form is explicitly defined as the transform thereof. In addition, the state of the transform mechanism after each such transform has occurred, must also be specified. The described method will also resolve the actual state that exists at the start of each document. It is also adapted to handle sub-documents, such as margin text, existing within a document to be transformed.

    8.
    发明专利
    未知

    公开(公告)号：BR8301430A

    公开(公告)日：1983-11-29

    申请号：BR8301430

    申请日：1983-03-21

    Applicant: IBM

    Inventor： AGNEW PALMER WRIGHT ,  BUONOMO JOSEPH PATRICK ,  HOUGHTALEN STEVEN RAY ,  KELLERMAN ANNE SHEILA ,  LOSINGER RAYMOND ELLISON ,  VALASHINAS JAMES WILLIAM

    IPC: G06F9/455 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

    Abstract: Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. The mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip.For each subset of the instructions that requires high performance, the corresponding microprocessor chip contains the data flow path and all elements, including registers, necessary for the execution of that subset as well as the microcode that controls execution. In some applications, a subset of the instructions that does not require high performance is implemented with a critical path that crosses several chip boundaries and is, therefore, considerably slower. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is ecomonically feasible to have several copies of a complex data flow and control store mechanism.

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