公开(公告)号：DE3381450D1

公开(公告)日：1990-05-17

申请号：DE3381450

申请日：1983-11-23

Applicant: IBM

Inventor： BUONOMO JOSEPH PATRICK ,  PERRY WENDELL LEE

IPC: G06F11/22 ,  G06F11/26

Abstract: A method for verifying the architectural integrity of a newly written or modified instruction set in a limited operating environment is described. More particularly, this methodology is adapted to perform such verification even though the processor under test (14) has only one or a few instructions in its partially complete instruction set. Such verification is accomplished using a minimum test driver, under control of a test support processor (10), which loads the data necessary to execute the instruction being tested, into a memory (12) shared for access by both processors (10, 14). The test system also provides actual or simulated l/O capabilities. After execution of that instruction, the test driver directs capture of the execution results for appropriate use. As an aid in performing the verification test, the test driver is provided with an invalid command that forces return of control to the test processor (10). In operation, the processor (14) to be microcoded is tested instruction by instruction, via shared memory (12), with microcode corrections being made on the same basis to avoid error propagation into the remainder of the instruction set as it is developed.

公开(公告)号：BR8301430A

公开(公告)日：1983-11-29

申请号：BR8301430

申请日：1983-03-21

Applicant: IBM

Inventor： AGNEW PALMER WRIGHT ,  BUONOMO JOSEPH PATRICK ,  HOUGHTALEN STEVEN RAY ,  KELLERMAN ANNE SHEILA ,  LOSINGER RAYMOND ELLISON ,  VALASHINAS JAMES WILLIAM

IPC: G06F9/455 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

Abstract: Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. The mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip.For each subset of the instructions that requires high performance, the corresponding microprocessor chip contains the data flow path and all elements, including registers, necessary for the execution of that subset as well as the microcode that controls execution. In some applications, a subset of the instructions that does not require high performance is implemented with a critical path that crosses several chip boundaries and is, therefore, considerably slower. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is ecomonically feasible to have several copies of a complex data flow and control store mechanism.

公开(公告)号：DE3485205D1

公开(公告)日：1991-11-28

申请号：DE3485205

申请日：1984-08-08

Applicant: IBM

Inventor： BUONOMO JOSEPH PATRICK ,  HOUGHTALEN STEVEN RAY ,  LOSINGER RAYMOND ELLISON ,  VALASHINAS JAMES WILLIAM

IPC: G06F9/455 ,  G06F9/26 ,  G06F9/318 ,  G06F9/38 ,  G06F15/16 ,  G06F9/44

Abstract: The performance of a multimicroprocessor implemented data processing system that emulates a mainframe is enhanced by providing a pair of override latches (32, 34) that serve to steer accesses between main and control storage for instruction fetch and operand acquisition in a manner that minimizes the complexity and size of microprocessor interface microcoding. This is achieved by connecting the instruction and operand override latches between a primary microprocessor (12), a secondary microprocessor (14), off-chip control storage (26) belonging to the secondary microprocessor, particularly memory mapped private storage therein, and main storage (24). The override latches are made responsive, via microcode provided for that purpose, to the type and cause of each memory access. The override latches are set or reset by a memory mapped write to a predefined address in the secondary control store after being enabled by control lines (48, 50) responsive to the particular microprocessor action being taken. When set, the instruction override latch directs all expected primary processor main storage instruction fetches to control store. When set, the operand override latch directs all expected primary processor main storage operand accesses to control store. As appropriate for instruction execution, either one or both of the the primary or secondary microprocessors can thereby be transparently latched to main or control storage.