公开(公告)号：JPH04251339A

公开(公告)日：1992-09-07

申请号：JP5238591

申请日：1991-03-18

Applicant: IBM

Inventor： AHARON AHARON ,  AYARU BAA DABUIDO ,  RAANAN GEUIRUTSUMAN ,  EMANIYUERU GOFUMAN ,  MOSHII REIBOUITSUTSU ,  BUIKUTAA SHIYUWARUTSUBAADO

IPC: G06F11/22 ,  G01R31/317 ,  G01R31/3183 ,  G06F11/30 ,  G06F17/50 ,  H03K3/84

Abstract: PURPOSE: To provide a dynamic method for generating a biased pseudo random test pattern, where the defect of a conventional still point method is conquested and which is for inspecting the function of an integrated circuit design. CONSTITUTION: Inspection is executed in a series of steps and respective test patterns provide whole data required for testing at least one of the inter-step circuit design of the steps. The respective steps are generated in two stages. In the first stage 1-13, the whole devices and parameters required for executing the respective steps are stipulated. In the second stage 14, the specified step is stipulated. The process is continued till the test pattern providing the number of the steps requested by a user is generated and also the test pattern is constituted by three parts finally. The initialized device stipulates an initial machine state and a test pattern execution part and the test pattern result part is generated by the value of the device which is changed during the execution of the respective steps.

公开(公告)号：JPH06332743A

公开(公告)日：1994-12-02

申请号：JP6598994

申请日：1994-04-04

Applicant: IBM

Inventor： AHARON AHARON ,  YOTSUSHI MARUKA ,  YOTSUSHI RIKUTENSUTEIN

IPC: G06F9/06 ,  G06F9/44 ,  G06F11/22 ,  G06F11/36

Abstract: PURPOSE: To provide a test program generator independent of an architecture for generatig a test program for checking the operation of a hardware processor on design. CONSTITUTION: This generator is provided with a means for storing data for indicating the instruction group and resources of a processor and the means for generating the test program from the stored data for the purpose of later storage or processing. The data are independent declaration items, the generator is provided with the means for extracting the data from the storage means and the relation of processor resources and semantic entity related to the respective instructions is modelled in the declaration items.

公开(公告)号：GB2278213A

公开(公告)日：1994-11-23

申请号：GB9310223

申请日：1993-05-18

Applicant: IBM

Inventor： AHARON AHARON ,  MALKA YOSSI ,  LICHTENSTEIN YOSSI

IPC: G06F9/06 ,  G06F9/44 ,  G06F11/22 ,  G06F11/36

Abstract: An architecture-independent test program generator for producing test programs for checking the operation of a hardware processor design comprises means for storing data representing the processor instruction set and resources, and logic (30) for generating test programs from said stored data, characterised in that the data is a separate declarative specification (10). The relationships between the processor resources and semantic entities associated with each instruction are modelled in the declarative specification.

公开(公告)号：DE69119972D1

公开(公告)日：1996-07-11

申请号：DE69119972

申请日：1991-03-21

Applicant: IBM

Inventor： AHARON AHARON ,  BAR-DAVID AYAL ,  GOFMAN EMANUEL DR ,  LEIBOWITZ MOSHE ,  SHWARTZBURD VICTOR ,  GEWIRTZMAN RAANAN

IPC: G06F11/22 ,  G01R31/317 ,  G01R31/3183 ,  G06F11/30 ,  G06F17/50 ,  H03K3/84 ,  G06F11/26 ,  G06F7/58

Abstract: In the dynamic process for the generation of biased pseudo-random test patterns for the functional verification of integrated circuit designs, the verification is performed in a sequence of steps, with each test pattern providing all data required to test a circuit design during at least one of said steps. Generation of each step is performed in two stages, where in a first stage all facilities and parameters required for the execution of the respective step are defined and assigned the proper values, and where in a second stage the execution of the particular step is performed. This process is continued until a test pattern with the number of steps requested by the user is generated, so that finally the test pattern comprises three parts: The initialized facilities define the initial machine state and execution parts of the test pattern, and the values of the facilities which have been changed during the execution of the steps, form the results part of the test pattern.

公开(公告)号：IL94115A

公开(公告)日：1996-06-18

申请号：IL9411590

申请日：1990-04-18

Applicant: IBM ISRAEL

Inventor： AHARON AHARON ,  BAR-DAVID AYAL ,  GEWIRTZMAN RAANAN ,  GOFMAN EMANUEL ,  LEIBOWITZ MOSHE ,  SHWARZBURD VICTOR

IPC: G06F11/22 ,  G01R31/317 ,  G01R31/3183 ,  G06F11/30 ,  G06F17/50 ,  H03K3/84 ,  G01R31/318 ,  G06F11/26 ,  G06F7/58

Abstract: In the dynamic process for the generation of biased pseudo-random test patterns for the functional verification of integrated circuit designs, the verification is performed in a sequence of steps, with each test pattern providing all data required to test a circuit design during at least one of said steps. Generation of each step is performed in two stages, where in a first stage all facilities and parameters required for the execution of the respective step are defined and assigned the proper values, and where in a second stage the execution of the particular step is performed. This process is continued until a test pattern with the number of steps requested by the user is generated, so that finally the test pattern comprises three parts: The initialized facilities define the initial machine state and execution parts of the test pattern, and the values of the facilities which have been changed during the execution of the steps, form the results part of the test pattern.