公开(公告)号：JP2000339221A

公开(公告)日：2000-12-08

申请号：JP2000135310

申请日：2000-05-09

Applicant: IBM

Inventor： ALBERT CHAN ,  SILHA EDWARD JOHN ,  THATCHER LARRY EDWARD ,  GU WAI-YAN YUN

IPC: G06F12/10

Abstract: PROBLEM TO BE SOLVED: To obtaen a device for invalidating a part of an ERAT entry by providing an address conversion device from a valid address to a real address and a circuit for selectively invalidating the entry of the address conversion device. SOLUTION: Misrequest registers 304, 306 and 308 validate EA of registers (EA) 303, (EA0) 305 and (EA1) 307 with respect to the arbitration register 313 of an LSU conversion device 300. The registers (EA) 303, (EA0) 305 and (EA1) 307 give the valid addresses received by an instruction fetch device 350 and an L/S device 201 to registers 310 to 312 in the LSU device 300. The arbitration register 313 selects one of addresses and sends it to SLB CAM 314. The SLB CAM 314 can be mounted as CAM. In such a mounting form, softwre invalidates an entry at need without directly writing the content of SLB.