公开(公告)号：JP2000339221A

公开(公告)日：2000-12-08

申请号：JP2000135310

申请日：2000-05-09

Applicant: IBM

Inventor： ALBERT CHAN ,  SILHA EDWARD JOHN ,  THATCHER LARRY EDWARD ,  GU WAI-YAN YUN

IPC: G06F12/10

Abstract: PROBLEM TO BE SOLVED: To obtaen a device for invalidating a part of an ERAT entry by providing an address conversion device from a valid address to a real address and a circuit for selectively invalidating the entry of the address conversion device. SOLUTION: Misrequest registers 304, 306 and 308 validate EA of registers (EA) 303, (EA0) 305 and (EA1) 307 with respect to the arbitration register 313 of an LSU conversion device 300. The registers (EA) 303, (EA0) 305 and (EA1) 307 give the valid addresses received by an instruction fetch device 350 and an L/S device 201 to registers 310 to 312 in the LSU device 300. The arbitration register 313 selects one of addresses and sends it to SLB CAM 314. The SLB CAM 314 can be mounted as CAM. In such a mounting form, softwre invalidates an entry at need without directly writing the content of SLB.

公开(公告)号：DE69419680T2

公开(公告)日：2000-03-02

申请号：DE69419680

申请日：1994-09-15

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNGS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/26

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：DE69419680D1

公开(公告)日：1999-09-02

申请号：DE69419680

申请日：1994-09-15

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNGS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/26

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：CA2107056C

公开(公告)日：1998-06-23

申请号：CA2107056

申请日：1993-09-27

Applicant: IBM

Inventor： OEHLER RICHARD RAPHAEL ,  KAHLE JAMES ALLAN ,  MUHICH JOHN STEPHEN ,  SILHA EDWARD JOHN

IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177

Abstract: A method and system are disclosed for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instructions and for performing read, write and store operations and an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses within the system memory. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields, an effective address and an associated real memory address for a selected system memory location. A reference bit is provided within a first individually accessible 5 in associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and this change bit is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate including accessible fields the reference bit and change bit may be concurrently updated by multiple processors, increasing memory concurrency.

公开(公告)号：BR9403514A

公开(公告)日：1995-06-20

申请号：BR9403514

申请日：1994-09-12

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNDS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/20

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.