公开(公告)号：US3749987A

公开(公告)日：1973-07-31

申请号：US3749987D

申请日：1971-08-09

Applicant: IBM

Inventor： ANANTHA N

IPC: H01L27/06 ,  H01L29/00 ,  H01L5/00

CPC classification number: H01L27/0688 ,  H01L27/0629 ,  H01L29/00 ,  Y10S148/008 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/122 ,  Y10S148/139

Abstract: A semiconductor device having at least one FET and at least one Schottky barrier diode. The device has an FET with source and drain regions in a semiconductor body and a gate electrode. The Schottky barrier diode consists of a thin layer of polycrystalline material separated from the semiconductor body by an insulating amorphous layer, an ohmic contact, and a barrier contact. The combination is particularly useful in fabricating logic and memory devices where the Schottky barrier diode is utilized as a resistance element and/or as an input output device. In the method of producing the device, a polysilicon layer is used to fabricate both the gate electrode and the Schottky barrier diode.

Abstract translation: 一种具有至少一个FET和至少一个肖特基势垒二极管的半导体器件。 该器件具有在半导体本体中具有源区和漏极区的FET和栅电极。 肖特基势垒二极管由通过绝缘非晶层，欧姆接触和屏障接触与半导体本体分离的多晶材料薄层组成。 该组合在制造逻辑和存储器件中特别有用，其中肖特基势垒二极管用作电阻元件和/或用作输入输出器件。 在制造该器件的方法中，使用多晶硅层来制造栅电极和肖特基势垒二极管。

公开(公告)号：BR7205403D0

公开(公告)日：1973-06-07

申请号：BR540372

申请日：1972-08-09

Applicant: IBM

Inventor： ANANTHA N

IPC: H01L27/10 ,  G11C16/04 ,  G11C27/04 ,  H01L21/339 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/762 ,  H01L19/00 ,  H01L7/00

公开(公告)号：BR7205394D0

公开(公告)日：1973-06-07

申请号：BR539472

申请日：1972-08-09

Applicant: IBM

Inventor： ANANTHA N

IPC: H01L27/10 ,  G11C16/04 ,  G11C27/04 ,  H01L21/339 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/762 ,  H01L19/00 ,  H01L7/00

公开(公告)号：BR7806949A

公开(公告)日：1979-05-15

申请号：BR7806949

申请日：1978-10-23

Applicant: IBM

Inventor： ANANTHA N ,  WALSH J ,  BHATIA H

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/32 ,  H01L29/08

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.