公开(公告)号：GB2523342A

公开(公告)日：2015-08-26

申请号：GB201403019

申请日：2014-02-20

Applicant: IBM

Inventor： ANGERER CHRISTOPH MARTIN ,  BEKAS KONSTANTINOS ,  DRAGONE SILVIO ,  POLIG RAPHAEL ,  HAGLEITNER CHRISTOPH ,  CURIONI ALESSANDRO

IPC: G06F17/12

Abstract: Conjugate gradient solver apparatus 2 is provided for generating data defining a solution vector x for a linear system represented by Ax = b where A is a predetermined matrix and b is a predetermined vector. Solver circuitry 6 of the apparatus processes input data, defining said matrix A and vector b, in accordance with an iterative conjugate gradient method to generate said data defining the solution vector x. The solver circuitry is adapted to process data items, corresponding to vectors used in said conjugate gradientmethod, having a variable fixed-point data format. A precision controller 7 of the apparatus determines the fixed-point data formats of respective said data items adaptively during progress of the conjugate gradient method in the solver circuitry 6. The solver apparatus may be implemented by a field programmable gate array (FPGA). The adaptive fixed-point format variation allows good results to be achieved while exploiting the simple, fast, and power-efficient operations available with fixed-point processing.

公开(公告)号：GB2523341A

公开(公告)日：2015-08-26

申请号：GB201403018

申请日：2014-02-20

Applicant: IBM

Inventor： ANGERER CHRISTOPH MARTIN ,  BEKAS KONSTANTINOS ,  DRAGONE SILVIO ,  GIEFERS HEINER ,  POLIG RAPHAEL ,  HAGLEITNER CHRISTOPH ,  CURIONI ALESSANDRO

IPC: G06F17/16 ,  G06F17/12

Abstract: An iIterative refinement apparatus is provided for generating data defining a solution vector x for a linear system represented by Ax = b, where A is a predetermined matrix and b is a predetermined vector. An outer solver (2, Fig 1) processes input data, defining the matrix A and vector b, in accordance with an outer loop of an iterative refinement method to generate said data defining the solution vector x. An inner solver (3, Fig 1) processes data items in accordance with an inner loop of the iterative refinement method. The inner solver is operable for processing said data items having variable bit-width and data format. A precision controller (4, Fig 1) determines the bit-widths and data formats of the data items adaptively in dependence on results of processing steps during progress of the iterative refinement method. The precision controller 4 is adapted to control operation of the inner solver 3 for processing said data items with the bit-widths and data formats so determined.

公开(公告)号：GB2521367A

公开(公告)日：2015-06-24

申请号：GB201322315

申请日：2013-12-17

Applicant: IBM

Inventor： ANGERER CHRISTOPH MARTIN ,  POLIG RAPHAEL

IPC: G06F9/45 ,  G06F9/455 ,  G06F9/50

Abstract: The processing of program code in a heterogeneous system is accelerated by optimizing a sequence of high-level instructions forming a code region at runtime. Regions are represented as dependency graphs, e.g. directed acyclic graphs, comprising segments 304-310 each assignable to a different processor, e.g. a graphic processor. The graphs are expanded via variants 406, 408, 410 of corresponding segments 306, 310. The variants can reverse the order of the functionalities of the associated segments, e.g. 410-406 instead of 306-310, or replace them with alternative functions, e.g. 408 instead of 306 or 406. For example, if 306/406 is a sort function, 408 can be a mergesort executable on available FPGAs. Segments are selected such that an equivalent code region is generated which minimizes a total cost function. Cost functions take account of speed or power consumption. The selected segments are assigned to their respective specific processors after being compiled at runtime.