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公开(公告)号:GB2530261A
公开(公告)日:2016-03-23
申请号:GB201416304
申请日:2014-09-16
Applicant: IBM
Inventor: GIEFERS HEINER , LUNTEREN JAN VAN
Abstract: A data processing system has data processing functionality in an execution unit, which is integrated into the memory system. An access processor sends data stored in the memory to the execution unit for processing. The access processor may send a tag with the data, identifying whether it is an operand or a configuration. The access processor uses the length of time taken to carry out the data processing operations in order to reserve time slots for the execution unit to write its results back into the memory. The access unit may send program information to the execution unit in order to configure it. The execution unit may be implemented as a field programmable gate array (FPGA). The memory may have a more than one execution unit and the some execution units may be more tightly coupled to the memory than others.
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公开(公告)号:GB2523341A
公开(公告)日:2015-08-26
申请号:GB201403018
申请日:2014-02-20
Applicant: IBM
Inventor: ANGERER CHRISTOPH MARTIN , BEKAS KONSTANTINOS , DRAGONE SILVIO , GIEFERS HEINER , POLIG RAPHAEL , HAGLEITNER CHRISTOPH , CURIONI ALESSANDRO
Abstract: An iIterative refinement apparatus is provided for generating data defining a solution vector x for a linear system represented by Ax = b, where A is a predetermined matrix and b is a predetermined vector. An outer solver (2, Fig 1) processes input data, defining the matrix A and vector b, in accordance with an outer loop of an iterative refinement method to generate said data defining the solution vector x. An inner solver (3, Fig 1) processes data items in accordance with an inner loop of the iterative refinement method. The inner solver is operable for processing said data items having variable bit-width and data format. A precision controller (4, Fig 1) determines the bit-widths and data formats of the data items adaptively in dependence on results of processing steps during progress of the iterative refinement method. The precision controller 4 is adapted to control operation of the inner solver 3 for processing said data items with the bit-widths and data formats so determined.
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