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公开(公告)号：JP2001075548A
公开(公告)日：2001-03-23
申请号：JP23531399
申请日：1999-08-23
Applicant: IBM
Inventor： YAMAUCHI KAZUSHI , HAYATA MASAYUKI
Abstract: PROBLEM TO BE SOLVED: To efficiently adjust the hue of a color to be displayed with a simple circuit. SOLUTION: In this hue adjusting method, (1), an input color such as that it's maximum value among R, G, B is the maxium gradation value (=L=2n-1) and it's minimum value is the minimum gradation value (=0) is converted into a color such as that it's maximum value among R, G, B is the maximum gradation value (=L=2n-1) and it's minimum value is the minimum gradation value (=0) based on the maximum conversion amount (= Atm) and a conversion direction. (2), an input color such as that it's maximum value among R, G, B is Dmax and it's minimum value is Dmin (provided, 0
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公开(公告)号：JP2001013937A
公开(公告)日：2001-01-19
申请号：JP16435499
申请日：1999-06-10
Applicant: IBM
Inventor： YAMASHITA HIROSHI , MINAMI TOSHIYA , IKEGAMI HIROYUKI , HAYATA MASAYUKI
Abstract: PROBLEM TO BE SOLVED: To attain easiness of extension by enabling many display devices to be chainingly connected in a state of which physical restrictions from respective devices are eliminated without changing the hardware of a system side. SOLUTION: This system is provided with a display driving device 1 outputting a video signal which is to be displayed with respect display areas and a chained display signal which is to be added to the video signal and also which uses at least the timing of one line, a first display device 2(1) capable of displaying a video with respect the display area of itself based on the video signal by inputting the video signal and the chained display signal and also by analyzing the chained display signal while being connected to the device 1 and a second display device 2(2) capable of displaying the video with respect to the display area of itself based on the video signal by inputting the video signal and the chained display signal and also by analyzing the chained display signal while being connected to the first display device 2(1).
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公开(公告)号：JPH08111789A
公开(公告)日：1996-04-30
申请号：JP23271994
申请日：1994-09-28
Applicant: IBM
Inventor： TSUJIMOTO HIROYUKI , HAYATA MASAYUKI , NISHIMURA KOICHI
Abstract: PURPOSE: To perform conversion to signals for stabilizing a processing in a PLL at all times even when the different kinds of composite synchronizing signals are inputted. CONSTITUTION: In a horizontal synchronization gate signal generation circuit 34, corresponding to characteristics inside a vertical synchronizing signal area, horizontal synchronization gate signals SHG for which a prescribed margin is added to the front and back of pulse signals obtained by the composite synchronizing signals CSH, cycle data and pulse width data, etc., are generated or the horizontal synchronization gate signals SHG for which the margin on a front side is canceled are generated inside the vertical synchronizing signal area recognized by vertical gate signals SVG. The horizontal synchronization gate signals SHG generated in such a manner are inputted to the second input terminal of an AND circuit 30 and ANDed with the composite synchronizing signals CSH inputted to a first input terminal and thus, horizontal synchronizing signals are surely obtained even inside the vertical synchronizing signal area.
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Patent Agency Ranking
公开(公告)号：JPH06334522A
公开(公告)日：1994-12-02
申请号：JP11445093
申请日：1993-05-17
Applicant: IBM
Inventor： YASUDA HIROAKI , INOUE KOJI , HAYATA MASAYUKI
Abstract: PURPOSE: To easily and optimally adjust the values of upper limit and lower limit reference voltages to be set in an A/D converter by user himself, without requiring a special device and to optimally A/D-convert only an original gradation part, even in an analog video signal provided with a blanking pedestal. CONSTITUTION: This device is constituted by providing lower limit and upper limit reference voltage adjusting circuits 10 and 12 for setting the lower limit and upper limit reference voltages of the A/D converter 4, where an analog video signal provided with a black level and a white level is inputted, an A/D output check circuit 14 for feeding-back a digital signal output from the A/D converter 4 and detecting the change point of time, when the level of the digital signal output is changed into the black level or the white level so as to output a detecting signal and a reference voltage adjustment control circuit 16 for supplying the upper limit and the lower limit reference voltages at the change point of time to the upper limit and the lower limit reference voltage adjusting circuit as the upper limit and lower limit reference voltage values according to the detecting signal.
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公开(公告)号：JPH05241545A
公开(公告)日：1993-09-21
申请号：JP31881391
申请日：1991-12-03
Applicant: IBM
Inventor： ASADA SHIGEKI , HAYATA MASAYUKI , YASUDA HIROAKI
Abstract: PURPOSE: To prevent the quality deterioration of images at different half-tone levels caused by the addition of a horizontal line or vertical column by providing an M-bit signal generating means and a means which supplies first and second sets of M-bit signals to a display device of a specific half-tone level. CONSTITUTION: The display system is provided with a means which generates first and second sets of M-bit signals respectively composed of PXQ pieces of signals and supplies the first and second sets of M-bit signals to an LCD device 25 at a 2M half-tone level. When operations are started from a picture element position (0, 0), a controller 12 first resets registers 1 and 4, an X counter 27, and Y counters 28 and 35. In this case, the controller 12 operates an odd column discriminating circuit 29, a line pattern generating circuit 36, and a comparator circuit 37, because the horizontal line of the LCD device 25 is added, namely, inserted. Therefore, the problem of image lines caused by dither tables 6-8 can be solved.
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公开(公告)号：JP2001083940A
公开(公告)日：2001-03-30
申请号：JP24358699
申请日：1999-08-30
Applicant: IBM
Inventor： YAMAUCHI KAZUSHI , HAYATA MASAYUKI
Abstract: PROBLEM TO BE SOLVED: To incarnate high-precision white point adjustment with a simple circuit formation based on efficient algorithm in a display system in full digital processing. SOLUTION: This device is equipped with a digital video interface 13 for inputting a digital video signal outputted from a host device, an adjustment value input means which is a liquid crystal display monitor 11 for executing color conversion without using a lookup table relative to the digital video signal inputted by the digital video interface 13, for inputting an adjustment value at a prescribed point relative to an achromatic color ranging from a maximum gradation achromatic color to a minimum gradation achromatic color, and a controller LSI22 for operating in the focusing direction of chromaticity coordinates in the achromatic color relative to the digital video signal inputted by the digital video interface 13 based on the adjustment value inputted by the adjustment value input means.
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公开(公告)号：JPH0898055A
公开(公告)日：1996-04-12
申请号：JP22783894
申请日：1994-09-22
Applicant: IBM
Inventor： NISHINO HIROZO , NISHIMURA KOICHI , HAYATA MASAYUKI
Abstract: PURPOSE: To avoid errors due to jitters, delays or the like in separating and taking out synchronizing signals from image signals to which synchronizing signals are added. CONSTITUTION: Sync-on-green signals are taken out from a branch line 56 branched on the way of a signal line 54 which connects an output terminal of a video amplifier 36 to an A/D converter 42, and are connected to an input terminal on the positive side of a comparator 58. It means that a voltage that is amplified by the video amplifier 36 and corresponds to luminance signal shifted by an offset voltage is inputted in an input terminal on the positive side of the comparator 58. On the other hand, to an input terminal on the negative side of the comparator 58 is inputted a threshold voltage for detecting falls of the above-mentioned synchronous signals. When a voltage corresponding to image signals becomes lower than the threshold voltage, the comparator 58 judges that synchronizing signals are detected and outputs a low level (L) signal.
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公开(公告)号：JPH02211521A
公开(公告)日：1990-08-22
申请号：JP3114789
申请日：1989-02-13
Applicant: IBM JAPAN
Inventor： IIDA HIROYASU , KODAIRA FUMIYA , NISHIOKA YOSHIO , HAYATA MASAYUKI
Abstract: PURPOSE:To load the large quantity of screen attribute data by reading the screen attribute data during a horizontal display period, setting them in a register with the use of a DMA function, and preventing character data from being displayed during the horizontal display period. CONSTITUTION:A bus controller 15 accesses a DMA row starting address in a row table area by a row table address signal in the last horizontal fly-back interval during a horizontal scanning fly-back interval. According to an accessed DMA row starting address, a DMA row in a display data area 9 is read in the horizontal display interval continuously after the horizontal fly-back interval. The screen attribute data on the read DMA row are supplied to the buffer of the controller 15, and supplied to a DMA controller 17 of a display controller 16 by a prescribed timing signal. The controller 17 DMA-transfered the set data and pallet data out of the supplied data respectively to an I/O register 18 and to the memory of a pallet mechanism 19.
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