公开(公告)号：DE2556831A1

公开(公告)日：1976-06-24

申请号：DE2556831

申请日：1975-12-17

Applicant: IBM

Inventor： ASKIN HALUK O ,  JACOBSON EDWARD C ,  LEE JAMES M ,  SONODA GEORGE

IPC: G11C11/412 ,  G11C7/00 ,  G11C11/40 ,  H01L29/76

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

公开(公告)号：FR2296243A1

公开(公告)日：1976-07-23

申请号：FR7534720

申请日：1975-11-05

Applicant: IBM

Inventor： ASKIN HALUK O ,  JACOBSON EDWARD C ,  LEE JAMES M ,  SONODA GEORGE

IPC: G11C11/412 ,  G11C11/40

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

公开(公告)号：DE3374254D1

公开(公告)日：1987-12-03

申请号：DE3374254

申请日：1983-11-03

Applicant: IBM

Inventor： ASKIN HALUK O ,  HO BRYANT K ,  RABBAT GUY

IPC: H03M5/16 ,  H03K19/018 ,  H03K19/20 ,  H04L25/49 ,  H03K19/092

公开(公告)号：CA1060994A

公开(公告)日：1979-08-21

申请号：CA237271

申请日：1975-10-08

Applicant: IBM

Inventor： ASKIN HALUK O ,  JACOBSON EDWARD C ,  LEE JAMES M ,  SONODA GEORGE

IPC: G11C7/02 ,  G11C11/24 ,  G11C11/40

Abstract: D.C. STABLE SEMICONDUCTOR MEMORY CELL Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's . The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

公开(公告)号：CA1033841A

公开(公告)日：1978-06-27

申请号：CA202286

申请日：1974-06-12

Applicant: IBM

Inventor： ASKIN HALUK O

IPC: G11C11/409 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4094

Abstract: Disclosed is a regeneration circuit for dynamic monolithic memories, wherein the signal output is very small and must be isolated from external noise during the refresh cycle. The present regeneration circuit includes an isolation transistor between the bit decoder and memory cell eliminating unnecessary bit line charging, reducing power requirements and noise, improving stability of the sense latch and increasing the speed of operation of the memory.