公开(公告)号：JP2000068276A

公开(公告)日：2000-03-03

申请号：JP10858599

申请日：1999-04-15

Applicant: IBM

Inventor： ASUM HESSEL ,  ERICH KLINK ,  JUERGEN KEHR ,  WENDEL DIETER ,  PASOTAM TORIKAM PATEL

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To obtain a VLSI(very large scale integration) circuit which reduces crosstalks between metal planes and in the metal plane of the VLSI circuit, and manufacture thereof. SOLUTION: One metal plane i+1 of a VLSI chip has a wiring 1, disposed according to the design of the chip and empty regions which have no wiring between metal lines. Channels which are not used in the empty regions are buried by voltage/ground lines 7 connected to a nearby plane (not shown). These segments are connected to voltage/ground buses 9 on a nearby plane i. The added voltage tracks and ground tracks shield wirings oriented in the same direction, to abruptly lessen the in-plane inter-line couplings or crosstalks. In addition, the inter-line coupling between vertical planes reduces approximately down to zero.