VLSI CIRCUIT AND MANUFACTURE THEREOF

    公开(公告)号:JP2000068276A

    公开(公告)日:2000-03-03

    申请号:JP10858599

    申请日:1999-04-15

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To obtain a VLSI(very large scale integration) circuit which reduces crosstalks between metal planes and in the metal plane of the VLSI circuit, and manufacture thereof. SOLUTION: One metal plane i+1 of a VLSI chip has a wiring 1, disposed according to the design of the chip and empty regions which have no wiring between metal lines. Channels which are not used in the empty regions are buried by voltage/ground lines 7 connected to a nearby plane (not shown). These segments are connected to voltage/ground buses 9 on a nearby plane i. The added voltage tracks and ground tracks shield wirings oriented in the same direction, to abruptly lessen the in-plane inter-line couplings or crosstalks. In addition, the inter-line coupling between vertical planes reduces approximately down to zero.

    SWITCHING CONFIGURATION AND METHOD PROVIDED WITH SEPARATE OUTPUT BUFFER

    公开(公告)号:JP2002141948A

    公开(公告)日:2002-05-17

    申请号:JP2001281049

    申请日:2001-09-17

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a switching configuration to transport a data packet including data packet destination information and a payload to one output port or more. SOLUTION: Each input port 20 of a switching device 10 has an output buffer 35 that stores a payload of each data packet arrived in each input port 20 to its address. Furthermore, each input port 20 is provided with output queues whose number is the same as that of output ports 30. Each output queue stores addresses of each payload stored in the output buffer 35 and they are classified depending on data packet destination information. The stored payload can be sent to at least one of the output ports 30 under the use of the stored addresses at the point of time and pointed out by the addresses.

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