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    MEMORY CIRCUIT AND ITS USE IN AN ELECTRICALLY PROGRAMMABLE LOGIC ARRAY
    1.
    发明专利
    MEMORY CIRCUIT AND ITS USE IN AN ELECTRICALLY PROGRAMMABLE LOGIC ARRAY 未知

    公开(公告)号：DE2963062D1

    公开(公告)日：1982-07-29

    申请号：DE2963062

    申请日：1979-06-01

    Applicant: IBM

    Inventor： BALASUBRAMANIAN PERUVEMBA S ,  GREENSPAN STEPHEN B

    IPC: G11C17/00 ,  G11C7/20 ,  G11C11/00 ,  G11C11/412 ,  G11C14/00 ,  G11C16/04 ,  G11C17/12 ,  H03K3/356 ,  H03K19/177 ,  G11C11/40 ,  H03K19/02 ,  H03K3/353

    Abstract: A write once, read only electrically programmable storage circuit is disclosed, which employs a flip-flop circuit to store the programmed conductive state of the array device, by means of a blocking transistor connected between the array device and one node of the flip-flop, the control electrode of the blocking transistor being connected to the other node of the flip-flop. With the flip-flop having an initial first state so that the blocking device is conductive, a precharged signal may be conducted through the array device to ground indicating a first stored information state. By driving a write signal through the array device and the blocking device, of sufficient magnitude to set the flip-flop in its opposite state, the blocking device is then made nonconductive and subsequent attempts to transmit a precharge signal through the array device to ground, will not be possible, indicating a second stored information state. This basic storage circuit is inclined as the array cell in a programmable PLA chip architecture which requires only four additional pins beyond the mask programmable version. This is accomplished by the dual use of the output latches of the OR array for both reading out the array and for programming the array by a scan-in technique. Cells in the AND array are programmed by a product term programmer register which allows product terms to be programmed by input partitioning circuits.

    ZERO OPTICAL PARALLAX STYLUS INTERFACE DEVICE
    2.
    发明专利
    ZERO OPTICAL PARALLAX STYLUS INTERFACE DEVICE 未知

    公开(公告)号：CA2056676A1

    公开(公告)日：1992-07-19

    申请号：CA2056676

    申请日：1991-11-29

    Applicant: IBM

    Inventor： BALASUBRAMANIAN PERUVEMBA S ,  COMERFORD LIAM D

    IPC: G02B6/12 ,  G06F3/033 ,  G06F3/041

    Abstract: YO9-90-123 ZERO OPTICAL PARALLAX STYLUS INTERFACE DEVICE An improved handwriting capture tablet has zero optical parallax allowing a highly accurate stylus driven computer-user interaction. The plane of contact of the stylus and the plane of the writing image are made to coincide, eliminating all optical parallax and resulting registration errors. This is accomplished by the use of an image transmission device, such as a fiber-optic face plate, to transmit the generated image to the stylus plane of contact.

    IR PULSE MODEM NRZI
    4.
    发明专利
    IR PULSE MODEM NRZI 未知

    公开(公告)号：PL179089B1

    公开(公告)日：2000-07-31

    申请号：PL31912595

    申请日：1995-09-15

    Applicant: IBM

    Inventor： BALASUBRAMANIAN PERUVEMBA S ,  LEE NATHAN J ,  LEKUCH SCOTT D

    IPC: H04L7/00 ,  H04L25/49 ,  H03M5/06 ,  H04B10/12

    Abstract: A modulation scheme and system, compatible with both the asynchronous IRDA mode and the synchronous mode of IR communication, involves Non-Return-to-Zero-Inverted (NRZI) and Flash pulse encoding in conjunction with zero-bit stuffing. A digital data stream has a zero-bit inserted therein, before NRZI format encoding, whenever five consecutive one's are detected in the stream to enable the controller to distinguish the data from flags, which are exempt from the zero-bit insertion, and to provide enough transitions in the data so that the demodulator's digital phase lock loop can stay locked independent of the data contents. A Flash pulse (of from +E,fra 3/16+EE to +E,fra 8/16+EE of bit cell width, depending on the data rate) is generated whenever a transition is detected in the NRZI formatted data. The result, in keeping with IRDA modulation, is that a Flash pulse is generated whenever a zero occurs in the data stream. On the demodulation side, whenever a Flash pulse is received, the level of the receive line is toggled resulting in an output in NRZI format. Using this modulation scheme with a serial controller which supports NRZI and bit-stuffing, a system may be constructed that uses the controller's phase lock loop to send and receive data synchronously.

    7.
    发明专利
    未知

    公开(公告)号：FR2395647A1

    公开(公告)日：1979-01-19

    申请号：FR7816944

    申请日：1978-05-29

    Applicant: IBM

    Inventor： BALASUBRAMANIAN PERUVEMBA S ,  BERTIN CLAUDE R ,  GREENSPAN STEPHEN B

    IPC: G06F11/267 ,  G11C17/12 ,  H01L21/82 ,  H01L27/112 ,  H03K19/177 ,  H03K19/20

    Abstract: A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array. A testing technique and special testing circuitry is disclosed which makes use of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage for the test response bits for individually testing both the AND components and the OR components in the merged array PLA.

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