中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.014 seconds)

    MEMORY CIRCUIT AND ITS USE IN AN ELECTRICALLY PROGRAMMABLE LOGIC ARRAY
    1.
    发明专利
    MEMORY CIRCUIT AND ITS USE IN AN ELECTRICALLY PROGRAMMABLE LOGIC ARRAY 未知

    公开(公告)号：DE2963062D1

    公开(公告)日：1982-07-29

    申请号：DE2963062

    申请日：1979-06-01

    Applicant: IBM

    Inventor： BALASUBRAMANIAN PERUVEMBA S ,  GREENSPAN STEPHEN B

    IPC: G11C17/00 ,  G11C7/20 ,  G11C11/00 ,  G11C11/412 ,  G11C14/00 ,  G11C16/04 ,  G11C17/12 ,  H03K3/356 ,  H03K19/177 ,  G11C11/40 ,  H03K19/02 ,  H03K3/353

    Abstract: A write once, read only electrically programmable storage circuit is disclosed, which employs a flip-flop circuit to store the programmed conductive state of the array device, by means of a blocking transistor connected between the array device and one node of the flip-flop, the control electrode of the blocking transistor being connected to the other node of the flip-flop. With the flip-flop having an initial first state so that the blocking device is conductive, a precharged signal may be conducted through the array device to ground indicating a first stored information state. By driving a write signal through the array device and the blocking device, of sufficient magnitude to set the flip-flop in its opposite state, the blocking device is then made nonconductive and subsequent attempts to transmit a precharge signal through the array device to ground, will not be possible, indicating a second stored information state. This basic storage circuit is inclined as the array cell in a programmable PLA chip architecture which requires only four additional pins beyond the mask programmable version. This is accomplished by the dual use of the output latches of the OR array for both reading out the array and for programming the array by a scan-in technique. Cells in the AND array are programmed by a product term programmer register which allows product terms to be programmed by input partitioning circuits.

    2.
    发明专利
    未知

    公开(公告)号：DE2826722A1

    公开(公告)日：1979-01-18

    申请号：DE2826722

    申请日：1978-06-19

    Applicant: IBM

    Inventor： BALASUBRAMANIAN PERUVEMBAS ,  BERTIN CLAUDE R ,  GREENSPAN STEPHEN B

    IPC: G06F11/267 ,  G11C17/12 ,  H01L21/82 ,  H01L27/112 ,  H03K19/177 ,  G06F7/00 ,  G11C9/00 ,  H01L27/08 ,  H03K19/00 ,  G06F9/00

    Abstract: A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array. A testing technique and special testing circuitry is disclosed which makes use of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage for the test response bits for individually testing both the AND components and the OR components in the merged array PLA.

    5.
    发明专利
    未知

    公开(公告)号：FR2395647A1

    公开(公告)日：1979-01-19

    申请号：FR7816944

    申请日：1978-05-29

    Applicant: IBM

    Inventor： BALASUBRAMANIAN PERUVEMBA S ,  BERTIN CLAUDE R ,  GREENSPAN STEPHEN B

    IPC: G06F11/267 ,  G11C17/12 ,  H01L21/82 ,  H01L27/112 ,  H03K19/177 ,  H03K19/20

    Abstract: A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array. A testing technique and special testing circuitry is disclosed which makes use of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage for the test response bits for individually testing both the AND components and the OR components in the merged array PLA.

Patent Agency Ranking