公开(公告)号：DE2826722A1

公开(公告)日：1979-01-18

申请号：DE2826722

申请日：1978-06-19

Applicant: IBM

Inventor： BALASUBRAMANIAN PERUVEMBAS ,  BERTIN CLAUDE R ,  GREENSPAN STEPHEN B

IPC: G06F11/267 ,  G11C17/12 ,  H01L21/82 ,  H01L27/112 ,  H03K19/177 ,  G06F7/00 ,  G11C9/00 ,  H01L27/08 ,  H03K19/00 ,  G06F9/00

Abstract: A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array. A testing technique and special testing circuitry is disclosed which makes use of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage for the test response bits for individually testing both the AND components and the OR components in the merged array PLA.

公开(公告)号：FR2395647A1

公开(公告)日：1979-01-19

申请号：FR7816944

申请日：1978-05-29

Applicant: IBM

Inventor： BALASUBRAMANIAN PERUVEMBA S ,  BERTIN CLAUDE R ,  GREENSPAN STEPHEN B

IPC: G06F11/267 ,  G11C17/12 ,  H01L21/82 ,  H01L27/112 ,  H03K19/177 ,  H03K19/20

Abstract: A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array. A testing technique and special testing circuitry is disclosed which makes use of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage for the test response bits for individually testing both the AND components and the OR components in the merged array PLA.