公开(公告)号：US3560810A

公开(公告)日：1971-02-02

申请号：US3560810D

申请日：1968-08-15

Applicant: IBM

Inventor： BALK PIETER ,  DONG DAVID W ,  ELDRIGE JEROME M

IPC: H01L29/78 ,  H01L21/316 ,  H01L29/00 ,  H01L29/51 ,  H01L11/14

CPC classification number: H01L29/511 ,  H01L21/316 ,  H01L29/00

Abstract: An insulated-gate field effect transistor is described which includes a gate insulator defined as a laminate structure comprising a phosphosilicate glass (PSG) layer and a silicon dioxide (SiO2) layer, the ratio of the thicknesses of such layers and, also, the P2O5 concentration in the PSG layer being properly chosen to insure stable device characteristics over extended periods under operation conditions.

公开(公告)号：DE1941279A1

公开(公告)日：1970-02-19

申请号：DE1941279

申请日：1969-08-13

Applicant: IBM

Inventor： BALK PIETER ,  WAH DONG DAVID ,  MICHAEL ELDRIDGE JEROME

IPC: H01L29/78 ,  H01L21/316 ,  H01L29/00 ,  H01L29/51 ,  H01L11/14

Abstract: 1,234,119. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 30 July, 1969 [15 Aug., 1968], No. 38207/69. Heading H1K. In an IGFET the insulating layer formed over the conduction channel 15 below the gate electrode 25 comprises a first layer of dielectric material 17, such as silicon dioxide, on the body of the IGFET and a second layer 19 of phosphosilicate glass formed over this first layer and directly under the gate electrode. The ratio of the thickness of the phosphosilicate glass layer to the thickness of the first layer of dielectric material is less than 3 and the combined thickness of the two layers is between 200 A and 1000 Š. Further, the phosphosilicate glass layer has a mole fraction of P 2 0 5 of less than 0-09. Aluminium electrodes are applied to allow electrical connections to the transistor.

公开(公告)号：CA783827A

公开(公告)日：1968-04-23

申请号：CA783827D

Applicant: IBM

Inventor： BALK PIETER ,  PILKUHN MANFRED H

公开(公告)号：CA868640A

公开(公告)日：1971-04-13

申请号：CA868640D

Applicant: IBM

Inventor： BALK PIETER ,  DONG DAVID W ,  ELDRIDGE JEROME M

公开(公告)号：DE1619969A1

公开(公告)日：1971-03-18

申请号：DE1619969

申请日：1967-06-30

Applicant: IBM

Inventor： BALK PIETER ,  YU NIEN ,  HAYES DILL FREDERICK

IPC: C30B31/18 ,  H01L21/00 ,  H01L21/316 ,  B01J17/34

公开(公告)号：CA832198A

公开(公告)日：1970-01-13

申请号：CA832198D

Applicant: IBM

Inventor： BALK PIETER ,  YU HWA N ,  DILL FREDERICK H JR

公开(公告)号：DE1489043A1

公开(公告)日：1969-05-14

申请号：DE1489043

申请日：1964-12-30

Applicant: IBM

Inventor： BALK PIETER ,  HEINRICH PILKUHN MANFRED

IPC: H01L29/267 ,  H01L29/43 ,  H01L29/778

Abstract: 1,038,900. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 1, 1964 [Dec. 30, 1963], No. 48679/64. Heading H1K. The channel of a unipolar transistor comprises a thin layer between two gate regions of different materials and opposite conductivity types, the channel being of the same material as one of the gate regions but of the opposite conductivity type. In a first embodiment, Fig. 1 (not shown), the device is fabricated by epitaxially depositing an N-type Ge region 3 from the vapour phase on to a P-type GaAs substrate 20 , an inversion layer 12 being formed which constitutes the channel. Ohmic contacts 5, 6, 7 and 8 are applied to the two gate regions and the ends of the channel respectively. As shown, Fig. 2, N-type Ge region 22 is formed on P-type GaAs substrate 20 forming P-type Ge inversion layer 27 which is contacted by P-type Ge source and drain regions 21 and 23. In a further embodiment, Fig. 3 (not shown), the channel comprises a thin P-type Ge layer 31 epitaxially deposited on a P-type GaAs substrate 30. The central portion of layer 31 is masked and deposition continued to produce thicker source and drain regions 32a, 32b, and N-type Ge is then deposited over the central portion to produce the second gate region 33. Complementary devices may also be produced.