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公开(公告)号:EP0634857A3
公开(公告)日:1998-05-13
申请号:EP94304281
申请日:1994-06-14
Applicant: IBM
Inventor: BARRACLOUGH KEITH ROBERT , GAY ADRIAN CHARLES
CPC classification number: H04N21/2368 , H04L12/1813 , H04L12/64 , H04M3/567 , H04N7/15 , H04N21/23614 , H04N21/4307 , H04N21/4341 , H04N21/4348
Abstract: The present invention relates a communication terminal for the synchronisation of audio and visual information within a communication system. Audio communication between the parties to a video conference is achieved by digitising the speech and transmitting the same over a packet based data network. Each party to the conference can draw the attention of the other party to an object on the screen using a pointer controlled by, say, a mouse or ball. The co-ordinates of each parties' pointer are incorporated, via a multiplexer, into the data packets containing the digitised speech and transmitted to the other party's terminal thereby ensuring the synchronisation the pointer information with the digitised speech.
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公开(公告)号:GB2281672A
公开(公告)日:1995-03-08
申请号:GB9318301
申请日:1993-09-03
Applicant: IBM
Inventor: BARRACLOUGH KEITH ROBERT , GAY ADRIAN CHARLES
IPC: H04N7/15
Abstract: In a video conference between a number N of parties, each video conferencing terminal produces a respective video signal comprising, in the case of the NTSC standard, sixty fields per second. These are input to an analog multi-point control unit which selects every Nth field from each input video signal and derives therefrom a single output video signal also of sixty fields per second, in which consecutive fields are derived cyclically from each of the N input video signals in turn. The single output video signal is transmitted to each video conferencing terminal, which separates out the fields of the input video signals present in the single output video signal to provide N individual reduced field rate video signals each comprising 60/N fields per second and each having fields derived from a respective one of the input video signals.
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公开(公告)号:GB2284968A
公开(公告)日:1995-06-21
申请号:GB9325924
申请日:1993-12-18
Applicant: IBM
Inventor: BARRACLOUGH KEITH ROBERT , CRIPPS PETER , GAY ADRIAN CHARLES
Abstract: A computer workstation receives multiple audio input streams over a network in an audio conference. The audio input streams are kept separate by storing them in different queues. Digital samples from each of the queues are transferred to an audio adapter card 28 for output. A digital signal processor 46 on the audio adapter card multiplies each audio stream by its own weighting parameter, before summing the audio streams together for output. Thus the relative volume of each of the audio output streams can be controlled. For each block of audio data, the volume is calculated and displayed to the user, allowing the user to see the volume in each audio input stream independently. The user is also provided with volume control for each audio input stream, which effectively adjusts the weighting parameter, thereby allowing the user to alter the relative volumes of each speaker in the conference.
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公开(公告)号:GB2278258A
公开(公告)日:1994-11-23
申请号:GB9310119
申请日:1993-05-17
Applicant: IBM
Inventor: JONES ALAN , GAY ADRIAN CHARLES , BARRACLOUGH KEITH ROBERT , CRIPPS PETER
IPC: G06F13/00 , H04L12/433 , H04L12/42
Abstract: A token ring local area network includes workstations running both conventional data and multimedia applications. The latter, which generally require a minimum throughput in order to be viable, can be split into two further categories: those which cannot tolerate excessive latency (end to end delay), typically interactive applications such as voice communications, and those which are less sensitive to latency, typically playback operations. the network recognises three priority levels: (1) for latency-sensitive multimedia applications, (2) for latency-insensitive multimedia applications, and (3) conventional applications. All multimedia applications prior to commencement of any communications over the LAN must request an allocation of throughput from a LAN segment resource manager (LSRM), which will only be awarded if there is currently sufficient available throughput on the LAN to support the attended communication. Furthermore, first priority level applications are also given a maximum token holding time, thereby ensuring rapid circulation of the token, and controlling latency.
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公开(公告)号:DE69428944T2
公开(公告)日:2002-07-04
申请号:DE69428944
申请日:1994-06-14
Applicant: IBM
Inventor: BARRACLOUGH KEITH ROBERT , GAY ADRIAN CHARLES
IPC: H04L29/06
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公开(公告)号:DE68916249D1
公开(公告)日:1994-07-21
申请号:DE68916249
申请日:1989-11-30
Applicant: IBM
IPC: G01R31/28 , G01R31/3185 , G06F1/04 , G06F1/10 , G06F11/22 , G11C19/00 , G01R31/318
Abstract: A logic circuit is presented comprising a plurality of registers 30, 39; each register 30 having first register latches 31, 41 for clocking data into the register 30 in response to a first clock signal 37 and second register latches for clocking data out of the register in response to a second clock signal 38, and combinatorial logic comprising address logic 4 for addressing data to a register and first suppression logic 33 for inhibiting the first clock signal input to the register in responsive to the address logic, wherein the logic circuit further comprises second suppression logic 34, 35 for inhibiting the second clock signal input to the register in collective response to the address logic and the first clock signal.
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公开(公告)号:DE69428944D1
公开(公告)日:2001-12-13
申请号:DE69428944
申请日:1994-06-14
Applicant: IBM
Inventor: BARRACLOUGH KEITH ROBERT , GAY ADRIAN CHARLES
IPC: H04L29/06
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公开(公告)号:DE68916249T2
公开(公告)日:1995-05-24
申请号:DE68916249
申请日:1989-11-30
Applicant: IBM
IPC: G01R31/28 , G01R31/3185 , G06F1/04 , G06F1/10 , G06F11/22 , G11C19/00 , G01R31/3177
Abstract: A logic circuit is presented comprising a plurality of registers 30, 39; each register 30 having first register latches 31, 41 for clocking data into the register 30 in response to a first clock signal 37 and second register latches for clocking data out of the register in response to a second clock signal 38, and combinatorial logic comprising address logic 4 for addressing data to a register and first suppression logic 33 for inhibiting the first clock signal input to the register in responsive to the address logic, wherein the logic circuit further comprises second suppression logic 34, 35 for inhibiting the second clock signal input to the register in collective response to the address logic and the first clock signal.
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公开(公告)号:GB2283153A
公开(公告)日:1995-04-26
申请号:GB9321907
申请日:1993-10-23
Applicant: IBM
Inventor: BARRACLOUGH KEITH ROBERT , GAY ADRIAN CHARLES , JONES ALAN L
IPC: H04M3/56 , H04M7/00 , H04L12/433
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公开(公告)号:GB2283152A
公开(公告)日:1995-04-26
申请号:GB9321527
申请日:1993-10-19
Applicant: IBM
Inventor: BARRACLOUGH KEITH ROBERT , GAY ADRIAN CHARLES
IPC: G06F3/16 , H04L12/64 , H04M9/02 , H04L12/433
Abstract: A computer workstation includes an audio adapter card for generating a sequence of digital audio data samples, aid accumulating them into audio data blocks. These are then transferred one at a time into a queue in the main memory of the computer workstation. A first program loop on the workstation receives an interrupt from the audio adapter card indicating the transfer of another audio data block, and maintains a record of the head of the queue. Another program loop requests access to the computer network, transmits messages from the workstation, and maintains a record of the tail of the queue. Each audio packet transmitted from the workstation incorporates essentially all the audio data currently enqueued.
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