公开(公告)号：DE3166256D1

公开(公告)日：1984-10-31

申请号：DE3166256

申请日：1981-03-23

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： BAZLEN DIETER DR ,  HAJDU JOHANN ,  KNAUFT GUNTER

IPC: G06F7/00 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G06F7/48 ,  G06F9/38

Abstract: The cycle time of a data processing system should always be determined in such a manner that data from a source register, after having been propagated through, if necessary, several transfer sections and line drivers, and through a chain of logic circuits for the respective processing steps, can be stored in the result or sink register safely and even with the worst case propagation tolerance of all elements involved. The ideal cycle time therefore, which is dependent on the processing speed of the slowest chain of logic circuits, has to have added time segments for the worst case of unprecise clocking. A reduction of the cycle time by the above mentioned added time segments, and if necessary by the propagation delays in the transfer sections and in the line drivers, is achieved when the chain of logic circuits and thus its delay time is divided into two partial chains with the partial delays and if the sink register is arranged between the two partial chains. By thus splitting the chain of logic circuits into two partial chains, the logic partial functions can be executed during that time segment which is composed of the above mentioned added time segments.

公开(公告)号：DE3072139D1

公开(公告)日：1989-02-02

申请号：DE3072139

申请日：1980-08-12

Applicant: IBM

Inventor： BAZLEN DIETER DR ,  BOCK DIETRICH ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  PAINKE HELMUT

IPC: G06F9/48 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/46

Abstract: In executing and controlling internal data flow for a particular program, it is often necessary to delay execution of an instruction by the insertion of an appropriate number of wait cycles. Thus, it may be necessary to interrupt instruction execution, for example, to insert a given number of wait cycles for channel access to common storage of the data processing system, for reloading a data or instruction buffer, or for a like situation. In such cases, the control unit has to ignore the particular instruction awaiting execution and execute another forced operation instead. An appropriate code is provided for a NO OPERATION instruction, say all bits zero. When a forced operation is to be executed, this code can be generated with fewer logic means at the output of the instruction register. As a result, there are no control signals active at the output of the decoder. The signals indicating forced operations have to be considered by the decoder only if a control signal is to be generated. If the control signals need be grouped for physical reasons, it is possible to determine which of these signals are a function of forced operations. This will negate the need to otherwise distribute these control signals throughout the decoder, thereby reducing and simplifying the wiring required.