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    Apparatus and method for using electrical fuses to store pll configuration data
    1.
    发明专利
    Apparatus and method for using electrical fuses to store pll configuration data 有权
    使用电熔丝存储PLL配置数据的装置和方法

    公开(公告)号：JP2007110711A

    公开(公告)日：2007-04-26

    申请号：JP2006271278

    申请日：2006-10-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BEATTIE IRENE ,  CHELSTROM NATHAN P ,  RILEY MACK W ,  FERNSLER MATTHEW E

    IPC: H03L7/06 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    CPC classification number: H03L7/06 ,  H03L7/10

    Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and a method for using electrical fuses to store PLL configuration data. SOLUTION: A portion of the electrical fuses 150 present in an integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and an electrical fuse controller 120 sense data at the portion of the electrical fuses 150 and direct serial transfer of the data to a PLL circuit 195 under the reference clock. When the transfer is complete, the power up controller directs a PLL logic to load the configuration data and start. Upon manufacturing, it is made possible to tailor a PLL default value on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL 195 may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL circuit 195 from the electrical fuses 150. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种使用电熔丝来存储PLL配置数据的装置和方法。 解决方案：集成电路中存在的一部分电保险丝150被保留用于PLL配置数据。 上电时，上电控制器和电熔丝控制器120在电保险丝150的部分处感测数据，并将数据直接串行传送到参考时钟下的PLL电路195。 传输完成后，上电控制器指示PLL逻辑来加载配置数据并启动。 在制造时，可以基于该设备的特性及其预期用途来定制给定设备上的PLL默认值。 因此，相同的PLL 195可以在相同或不同的架构中使用，以便基于从电保险丝150传递到PLL电路195的配置数据来执行不同的操作。（C）2007，JPO＆INPIT

    METHOD AND CIRCUIT ARRANGEMENT FOR SELECTIVE CONTROL OF WINDOW RELATED OVERLAY AND UNDERLAY PATTERNS
    4.
    发明专利
    METHOD AND CIRCUIT ARRANGEMENT FOR SELECTIVE CONTROL OF WINDOW RELATED OVERLAY AND UNDERLAY PATTERNS 未知

    公开(公告)号：HUT65611A

    公开(公告)日：1994-07-28

    申请号：HU126293

    申请日：1991-10-29

    Applicant: IBM

    Inventor： DESAI NARENDRA M ,  BEATTIE IRENE ,  VANOVER MICHAEL TERRELL ,  VOLTIN JOHN ALVIN

    IPC: G06T11/00 ,  G09G5/06 ,  G06F3/14 ,  G09G5/14

    Abstract: A video display system selectively controls by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics display. A logic/multiplex control 13, 11 translates overlay and underlay data patterns from a multiple plane VRAM 12, referenced to the graphics system frame buffer 9, into window specific patterns. The window related translation is conveyed to conventional RAMDACs 11 for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamicaliy written into a random access memory 14, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.

    METHOD OF AND APPARATUS FOR GENERATING IMAGES IN A CTR DISPAY UNIT
    5.
    发明专利
    METHOD OF AND APPARATUS FOR GENERATING IMAGES IN A CTR DISPAY UNIT 未知

    公开(公告)号：PL167318B1

    公开(公告)日：1995-08-31

    申请号：PL29893791

    申请日：1991-10-29

    Applicant: IBM

    Inventor： BEATTIE IRENE ,  DESAI NARENDRA M ,  VANOVER MICHAEL T ,  VOLTIN JOHN A

    IPC: G06T11/00 ,  G09G5/06 ,  G06F3/14 ,  G09G5/14

    Abstract: A video display system selectively controls by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics display. A logic/multiplex control 13, 11 translates overlay and underlay data patterns from a multiple plane VRAM 12, referenced to the graphics system frame buffer 9, into window specific patterns. The window related translation is conveyed to conventional RAMDACs 11 for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamicaliy written into a random access memory 14, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.

    7.
    发明专利
    未知

    公开(公告)号：DE69109241T2

    公开(公告)日：1995-11-02

    申请号：DE69109241

    申请日：1991-10-14

    Applicant: IBM

    Inventor： BEATTIE IRENE ,  DESAI NARENDRA M ,  VANOVER MICHAEL TERRELL ,  VOLTIN JOHN ALVIN

    IPC: G06F3/14 ,  G06T11/00 ,  G09G5/06 ,  G09G5/14

    Abstract: A video display system selectively controls by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics display. A logic/multiplex control 13, 11 translates overlay and underlay data patterns from a multiple plane VRAM 12, referenced to the graphics system frame buffer 9, into window specific patterns. The window related translation is conveyed to conventional RAMDACs 11 for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamicaliy written into a random access memory 14, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.

    8.
    发明专利
    未知

    公开(公告)号：DE69109241D1

    公开(公告)日：1995-06-01

    申请号：DE69109241

    申请日：1991-10-14

    Applicant: IBM

    Inventor： BEATTIE IRENE ,  DESAI NARENDRA M ,  VANOVER MICHAEL TERRELL ,  VOLTIN JOHN ALVIN

    IPC: G06F3/14 ,  G06T11/00 ,  G09G5/06 ,  G09G5/14

    Abstract: A video display system selectively controls by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics display. A logic/multiplex control 13, 11 translates overlay and underlay data patterns from a multiple plane VRAM 12, referenced to the graphics system frame buffer 9, into window specific patterns. The window related translation is conveyed to conventional RAMDACs 11 for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamicaliy written into a random access memory 14, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.

    SELECTIVE CONTROL OF WINDOW RELATED OVERLAYS AND UNDERLAYS
    10.
    发明专利
    SELECTIVE CONTROL OF WINDOW RELATED OVERLAYS AND UNDERLAYS 未知

    公开(公告)号：CA2053988A1

    公开(公告)日：1992-05-16

    申请号：CA2053988

    申请日：1991-10-22

    Applicant: IBM

    Inventor： BEATTIE IRENE ,  DESAI NARENDRA M ,  VANOVER MICHAEL T ,  VOLTIN JOHN A

    IPC: G06F3/14 ,  G06T11/00 ,  G09G5/06 ,  G09G5/14

    Abstract: A video display system selectively controls by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics display. A logic/multiplex control 13, 11 translates overlay and underlay data patterns from a multiple plane VRAM 12, referenced to the graphics system frame buffer 9, into window specific patterns. The window related translation is conveyed to conventional RAMDACs 11 for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamicaliy written into a random access memory 14, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.

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