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    3.
    发明专利
    未知

    公开(公告)号：DE69109241T2

    公开(公告)日：1995-11-02

    申请号：DE69109241

    申请日：1991-10-14

    Applicant: IBM

    Inventor： BEATTIE IRENE ,  DESAI NARENDRA M ,  VANOVER MICHAEL TERRELL ,  VOLTIN JOHN ALVIN

    IPC: G06F3/14 ,  G06T11/00 ,  G09G5/06 ,  G09G5/14

    Abstract: A video display system selectively controls by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics display. A logic/multiplex control 13, 11 translates overlay and underlay data patterns from a multiple plane VRAM 12, referenced to the graphics system frame buffer 9, into window specific patterns. The window related translation is conveyed to conventional RAMDACs 11 for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamicaliy written into a random access memory 14, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.

    4.
    发明专利
    未知

    公开(公告)号：DE69109241D1

    公开(公告)日：1995-06-01

    申请号：DE69109241

    申请日：1991-10-14

    Applicant: IBM

    Inventor： BEATTIE IRENE ,  DESAI NARENDRA M ,  VANOVER MICHAEL TERRELL ,  VOLTIN JOHN ALVIN

    IPC: G06F3/14 ,  G06T11/00 ,  G09G5/06 ,  G09G5/14

    Abstract: A video display system selectively controls by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics display. A logic/multiplex control 13, 11 translates overlay and underlay data patterns from a multiple plane VRAM 12, referenced to the graphics system frame buffer 9, into window specific patterns. The window related translation is conveyed to conventional RAMDACs 11 for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamicaliy written into a random access memory 14, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.

    MACHINE TOOL CONTROLLER
    6.
    发明专利
    MACHINE TOOL CONTROLLER 未知

    公开(公告)号：AU7742481A

    公开(公告)日：1982-05-27

    申请号：AU7742481

    申请日：1981-11-12

    Applicant: IBM

    Inventor： ASHFORD THOMAS JAY ,  KRISHNAMURTY RAJAN ,  VOLTIN JOHN ALVIN

    IPC: G06F11/22 ,  G05B19/4063 ,  G06F11/26 ,  G06F11/267 ,  G06F13/00 ,  G09B9/00 ,  B23Q15/00 ,  G06F11/30

    Abstract: In a system for controlling a machine tool (12) by a tool controller (10) under the supervision of a central data processor (11), in which the controller (10) transforms the data provided by the central processor (11) into a format compatible with the machine tool (12), e.g., clock pulse encoded data format suitable for writing into and reading out of a serial storage magnetic memory device (12), a test system is provided wherein the central processor (11) includes a simulation of the controller (10). This simulated controller gives the processor the capability of simulating and applying to the tool controller (10) data in a format equivalent to that normally applied to the tool controller from the tool (12) itself, e.g., a clock encoded data read output. The simulated controller also provides the central processor with the capability of receiving from the tool controller a tool control output in the format compatible with the tool control, e.g., clock encoded data and changing said data into an original format usable in the central processor.

    APPARATUS AND METHOD FOR MERGING PIXELS
    7.
    发明专利
    APPARATUS AND METHOD FOR MERGING PIXELS 未知

    公开(公告)号：CA2372109A1

    公开(公告)日：2001-01-11

    申请号：CA2372109

    申请日：2000-05-22

    Applicant: IBM

    Inventor： SPANNAUS JOHN FRED ,  VOLTIN JOHN ALVIN

    IPC: G06F3/14 ,  G06T1/20 ,  G09G5/00 ,  G09G5/36

    Abstract: A pixel merge apparatus and method has been implemented. Included is a configurable graphics device, which may serve as a standalone graphics engin e, or as a master or slave in a master/slave configuration. In stand alone mode , the mechanism drives a display device with native pixel data. A device configured in master mode is operable for receiving pixel data from a corresponding slave device, and merging the slave pixel data with native pix el data generated by a rasterizer within the ASIC. Data is communicated between slave and master using a digital data link which may also serve to drive a flat panel display in standalone mode. A FIFO, active in the master, mediate s the transfer of the slave pixel data and permits switching between native an d slave pixel data with signal pixel resolution. Pixel data may be merged on a frame-by-frame basis, or in split frame mode wherein a first portion of the graphic shown on a display device constitutes native pixels generated in the rasterizer corresponding to the master device, and a second portion of the displayed graphic includes pixels generated by the rasterizer in the slave device.

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