公开(公告)号：DE69016018T2

公开(公告)日：1995-07-06

申请号：DE69016018

申请日：1990-08-10

Applicant: IBM

Inventor： BEAULIEU CESCA JOSEPH ,  CALVIGNAC JEAN LOUIS ,  MILLET JEAN-MARC ,  NAUDIN BERNARD

IPC: G06F13/00 ,  H04L1/16 ,  H04L1/18 ,  H04L29/06 ,  H04L29/08

Abstract: The mechanism of the subject invention provides for an efficient interface between the hardware parts and software parts of communication modules used in a communication node wherein one module communicates with another module through a very high speed communication media. It insures the integrity of the data messages transferred between modules without impairing the performance of the data transfers. To deal with the problem of data message integrity at a very high speed, data link control DLC protocol relevant to steady state functions is implemented in hardware by finite state machines in the data store interfaces 14 and software running in microprocessor 16 is in charge of the initialization and recovery procedures.The steady functions are implemented by the hardware using sets of indicators in a request table which are representative of the transfer conditions, control blocks SCB which are representative of the transmission protocol variables and a message parameter/status field to carry the xmission protocol variables relevant to the message to the destination node. If an error is detected by the hardware part the indicators allows to freeze the operations of the hardware in order the microprocessor performs the error recovery functions using the transmission protocol variables in the control blocks.

公开(公告)号：DE69016018D1

公开(公告)日：1995-02-23

申请号：DE69016018

申请日：1990-08-10

Applicant: IBM

Inventor： BEAULIEU CESCA JOSEPH ,  CALVIGNAC JEAN LOUIS ,  MILLET JEAN-MARC ,  NAUDIN BERNARD

IPC: G06F13/00 ,  H04L1/16 ,  H04L1/18 ,  H04L29/06 ,  H04L29/08

Abstract: The mechanism of the subject invention provides for an efficient interface between the hardware parts and software parts of communication modules used in a communication node wherein one module communicates with another module through a very high speed communication media. It insures the integrity of the data messages transferred between modules without impairing the performance of the data transfers. To deal with the problem of data message integrity at a very high speed, data link control DLC protocol relevant to steady state functions is implemented in hardware by finite state machines in the data store interfaces 14 and software running in microprocessor 16 is in charge of the initialization and recovery procedures.The steady functions are implemented by the hardware using sets of indicators in a request table which are representative of the transfer conditions, control blocks SCB which are representative of the transmission protocol variables and a message parameter/status field to carry the xmission protocol variables relevant to the message to the destination node. If an error is detected by the hardware part the indicators allows to freeze the operations of the hardware in order the microprocessor performs the error recovery functions using the transmission protocol variables in the control blocks.