公开(公告)号：DE69016018D1

公开(公告)日：1995-02-23

申请号：DE69016018

申请日：1990-08-10

Applicant: IBM

Inventor： BEAULIEU CESCA JOSEPH ,  CALVIGNAC JEAN LOUIS ,  MILLET JEAN-MARC ,  NAUDIN BERNARD

IPC: G06F13/00 ,  H04L1/16 ,  H04L1/18 ,  H04L29/06 ,  H04L29/08

Abstract: The mechanism of the subject invention provides for an efficient interface between the hardware parts and software parts of communication modules used in a communication node wherein one module communicates with another module through a very high speed communication media. It insures the integrity of the data messages transferred between modules without impairing the performance of the data transfers. To deal with the problem of data message integrity at a very high speed, data link control DLC protocol relevant to steady state functions is implemented in hardware by finite state machines in the data store interfaces 14 and software running in microprocessor 16 is in charge of the initialization and recovery procedures.The steady functions are implemented by the hardware using sets of indicators in a request table which are representative of the transfer conditions, control blocks SCB which are representative of the transmission protocol variables and a message parameter/status field to carry the xmission protocol variables relevant to the message to the destination node. If an error is detected by the hardware part the indicators allows to freeze the operations of the hardware in order the microprocessor performs the error recovery functions using the transmission protocol variables in the control blocks.

公开(公告)号：DE3850881T2

公开(公告)日：1995-03-09

申请号：DE3850881

申请日：1988-10-28

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  LIPS JEAN-PIERRE ,  MILLET JEAN-MARC ,  MUNIER JEAN-MARIE ,  NAUDIN BERNARD

IPC: G06F15/16 ,  G06F13/38 ,  G06F13/42 ,  G06F15/167 ,  G06F15/177

Abstract: The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. The messages are received by memory interface 22 from the source users and then are enqueued in link inbound queues (LIQ) which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface 22 sends a dequeue order request to the centralized control means, said request identifying the corresponding user queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface 22 sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by memory interface 22.

公开(公告)号：DE3850881D1

公开(公告)日：1994-09-01

申请号：DE3850881

申请日：1988-10-28

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  LIPS JEAN-PIERRE ,  MILLET JEAN-MARC ,  MUNIER JEAN-MARIE ,  NAUDIN BERNARD

IPC: G06F15/16 ,  G06F13/38 ,  G06F13/42 ,  G06F15/167 ,  G06F15/177

Abstract: The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. The messages are received by memory interface 22 from the source users and then are enqueued in link inbound queues (LIQ) which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface 22 sends a dequeue order request to the centralized control means, said request identifying the corresponding user queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface 22 sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by memory interface 22.

公开(公告)号：CA1320590C

公开(公告)日：1993-07-20

申请号：CA607308

申请日：1989-08-02

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  LIPS JEAN-PIERRE ,  MILLET JEAN-MARC ,  MUNIER JEAN-MARIE ,  NAUDIN BERNARD

IPC: G06F15/16 ,  G06F13/38 ,  G06F13/42 ,  G06F15/167 ,  G06F15/177

Abstract: MECHANISM FOR TRANSFERRING MESSAGES BETWEEN SOURCE AND DESTINATION USERS THROUGH A SHAPED MEMORY The present invention relates to a mechanism for managing a memory shared between a number of users, so that the users may exchange messages through the memory, in a performant way. The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. Messages are received by a memory interface from source users and then are enqueued in link inbound queues which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process, enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface sends a dequeue order request to the centralized control means, said request identifying the corresponding user FR9-88-009 queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by the memory interface. FR9-88-009

公开(公告)号：DE69016018T2

公开(公告)日：1995-07-06

申请号：DE69016018

申请日：1990-08-10

Applicant: IBM

Inventor： BEAULIEU CESCA JOSEPH ,  CALVIGNAC JEAN LOUIS ,  MILLET JEAN-MARC ,  NAUDIN BERNARD

IPC: G06F13/00 ,  H04L1/16 ,  H04L1/18 ,  H04L29/06 ,  H04L29/08

Abstract: The mechanism of the subject invention provides for an efficient interface between the hardware parts and software parts of communication modules used in a communication node wherein one module communicates with another module through a very high speed communication media. It insures the integrity of the data messages transferred between modules without impairing the performance of the data transfers. To deal with the problem of data message integrity at a very high speed, data link control DLC protocol relevant to steady state functions is implemented in hardware by finite state machines in the data store interfaces 14 and software running in microprocessor 16 is in charge of the initialization and recovery procedures.The steady functions are implemented by the hardware using sets of indicators in a request table which are representative of the transfer conditions, control blocks SCB which are representative of the transmission protocol variables and a message parameter/status field to carry the xmission protocol variables relevant to the message to the destination node. If an error is detected by the hardware part the indicators allows to freeze the operations of the hardware in order the microprocessor performs the error recovery functions using the transmission protocol variables in the control blocks.

公开(公告)号：DE68920740D1

公开(公告)日：1995-03-02

申请号：DE68920740

申请日：1989-09-20

Applicant: IBM

Inventor： LIPS JEAN-PIERRE ,  MILLET JEAN-MARC ,  NAUDIN BERNARD

IPC: G06F12/02 ,  G06F5/10 ,  G06F5/12 ,  G06F12/00 ,  G06F13/00 ,  G06F5/06

Abstract: The subject device manages the access to message queues in a memory (6) by an enqueuer 2 and a degiieuer 7 when the enqueuer has priority over the dequeuer. It solves the contention problem raised when the dequeuer dequeues the last message from a queue while the enqueuer is enqueuing a new one. A queue control block QCB and queue status bits E, A, D are assigned to each queue and stored in memories 20 and 22. Each time dequeuer 7 performs a dequeuing operation it sets its D bit (dequeuer active) before updating the queue head field in the QCB block. When the enqueuer performs an enqueuing operation it sets an abort bit A, if it founds the D bit active and E bit active indicating that the queue contains at least one message to warn the dequeuer that it has to abort its proces if it is dequeuing the last message from the queue.