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公开(公告)号：DE69016018D1
公开(公告)日：1995-02-23
申请号：DE69016018
申请日：1990-08-10
Applicant: IBM
Inventor： BEAULIEU CESCA JOSEPH , CALVIGNAC JEAN LOUIS , MILLET JEAN-MARC , NAUDIN BERNARD
Abstract: The mechanism of the subject invention provides for an efficient interface between the hardware parts and software parts of communication modules used in a communication node wherein one module communicates with another module through a very high speed communication media. It insures the integrity of the data messages transferred between modules without impairing the performance of the data transfers. To deal with the problem of data message integrity at a very high speed, data link control DLC protocol relevant to steady state functions is implemented in hardware by finite state machines in the data store interfaces 14 and software running in microprocessor 16 is in charge of the initialization and recovery procedures.The steady functions are implemented by the hardware using sets of indicators in a request table which are representative of the transfer conditions, control blocks SCB which are representative of the transmission protocol variables and a message parameter/status field to carry the xmission protocol variables relevant to the message to the destination node. If an error is detected by the hardware part the indicators allows to freeze the operations of the hardware in order the microprocessor performs the error recovery functions using the transmission protocol variables in the control blocks.
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公开(公告)号：DE68919696T2
公开(公告)日：1995-05-24
申请号：DE68919696
申请日：1989-09-26
Applicant: IBM
Inventor： CALVIGNAC JEAN CALVIGNAC JEAN , FERAUD JACQUES , LIPS JEAN-PIERRE , NAUDIN BERNARD , SAINT-GEORGES ERIC
Abstract: The subject distribution mechanism is used in a communication system comprising a plurality of interfaces, (10, 11 ans 12) with each interface connected to at least one user and able to receive and transmit information to said user(s) through information carrying means. It allows communications to be established between users selected by a central control unit (7) in a programmable way. The distribution mechanism comprises: in each interface, scheduling means responsive to a common timing signal having a period T, to divide the period into n slot periods having a slot number, n being the number of users connected to that interface to which the maximum number of users are connected, a configuration table (18) comprising n locations, each location assigned to a slot period, the central control unit writing in each location communication control information, said table being addressed by the slot numbers generated by the scheduling means to read and make available, the communication control information, distribution buffer means (20) comprising at least a first and a second part, each part having n addressable locations, addressed by means of addressing means responsive to the communication control information provided by the configuration table during each slot period to cause each interface involved in the to be established communications during that slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot number generated by the scheduling means.
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公开(公告)号：DE69016018T2
公开(公告)日：1995-07-06
申请号：DE69016018
申请日：1990-08-10
Applicant: IBM
Inventor： BEAULIEU CESCA JOSEPH , CALVIGNAC JEAN LOUIS , MILLET JEAN-MARC , NAUDIN BERNARD
Abstract: The mechanism of the subject invention provides for an efficient interface between the hardware parts and software parts of communication modules used in a communication node wherein one module communicates with another module through a very high speed communication media. It insures the integrity of the data messages transferred between modules without impairing the performance of the data transfers. To deal with the problem of data message integrity at a very high speed, data link control DLC protocol relevant to steady state functions is implemented in hardware by finite state machines in the data store interfaces 14 and software running in microprocessor 16 is in charge of the initialization and recovery procedures.The steady functions are implemented by the hardware using sets of indicators in a request table which are representative of the transfer conditions, control blocks SCB which are representative of the transmission protocol variables and a message parameter/status field to carry the xmission protocol variables relevant to the message to the destination node. If an error is detected by the hardware part the indicators allows to freeze the operations of the hardware in order the microprocessor performs the error recovery functions using the transmission protocol variables in the control blocks.
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公开(公告)号：DE68920740D1
公开(公告)日：1995-03-02
申请号：DE68920740
申请日：1989-09-20
Applicant: IBM
Inventor： LIPS JEAN-PIERRE , MILLET JEAN-MARC , NAUDIN BERNARD
Abstract: The subject device manages the access to message queues in a memory (6) by an enqueuer 2 and a degiieuer 7 when the enqueuer has priority over the dequeuer. It solves the contention problem raised when the dequeuer dequeues the last message from a queue while the enqueuer is enqueuing a new one. A queue control block QCB and queue status bits E, A, D are assigned to each queue and stored in memories 20 and 22. Each time dequeuer 7 performs a dequeuing operation it sets its D bit (dequeuer active) before updating the queue head field in the QCB block. When the enqueuer performs an enqueuing operation it sets an abort bit A, if it founds the D bit active and E bit active indicating that the queue contains at least one message to warn the dequeuer that it has to abort its proces if it is dequeuing the last message from the queue.
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公开(公告)号：DE3883528T2
公开(公告)日：1994-03-17
申请号：DE3883528
申请日：1988-06-16
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , NAUDIN BERNARD , PIN CLAUDE LES JARDINS DE CESS , SAINT-GEORGES ERIC
Abstract: This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6.
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Patent Agency Ranking
公开(公告)号：DE68919696D1
公开(公告)日：1995-01-12
申请号：DE68919696
申请日：1989-09-26
Applicant: IBM
Inventor： CALVIGNAC JEAN CALVIGNAC JEAN , FERAUD JACQUES , LIPS JEAN-PIERRE , NAUDIN BERNARD , SAINT-GEORGES ERIC
Abstract: The subject distribution mechanism is used in a communication system comprising a plurality of interfaces, (10, 11 ans 12) with each interface connected to at least one user and able to receive and transmit information to said user(s) through information carrying means. It allows communications to be established between users selected by a central control unit (7) in a programmable way. The distribution mechanism comprises: in each interface, scheduling means responsive to a common timing signal having a period T, to divide the period into n slot periods having a slot number, n being the number of users connected to that interface to which the maximum number of users are connected, a configuration table (18) comprising n locations, each location assigned to a slot period, the central control unit writing in each location communication control information, said table being addressed by the slot numbers generated by the scheduling means to read and make available, the communication control information, distribution buffer means (20) comprising at least a first and a second part, each part having n addressable locations, addressed by means of addressing means responsive to the communication control information provided by the configuration table during each slot period to cause each interface involved in the to be established communications during that slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot number generated by the scheduling means.
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公开(公告)号：DE3883528D1
公开(公告)日：1993-09-30
申请号：DE3883528
申请日：1988-06-16
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , NAUDIN BERNARD , PIN CLAUDE LES JARDINS DE CESS , SAINT-GEORGES ERIC
Abstract: This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6.
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公开(公告)号：DE3850881T2
公开(公告)日：1995-03-09
申请号：DE3850881
申请日：1988-10-28
Applicant: IBM
Inventor： CALVIGNAC JEAN , LIPS JEAN-PIERRE , MILLET JEAN-MARC , MUNIER JEAN-MARIE , NAUDIN BERNARD
IPC: G06F15/16 , G06F13/38 , G06F13/42 , G06F15/167 , G06F15/177
Abstract: The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. The messages are received by memory interface 22 from the source users and then are enqueued in link inbound queues (LIQ) which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface 22 sends a dequeue order request to the centralized control means, said request identifying the corresponding user queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface 22 sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by memory interface 22.
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公开(公告)号：CA2018068C
公开(公告)日：1994-09-06
申请号：CA2018068
申请日：1990-06-01
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , LIPS JEAN-PIERRE , NAUDIN BERNARD , SAINT-GEORGES ERIC
Abstract: The subject distribution mechanism is used in a communication system comprising a plurality of interfaces, (10, 11 and 12) with each interface connected to at least one user and able to receive and transmit information to said user(s) through information carrying means. It allows communications to be established between users selected by a central control unit (7) in a programmable way. The distribution mechanism comprises: in each interface, scheduling means responsive to a common timing signal having a period T, to divide the period into n slot periods having a slot number, n being the number of users connected to that interface to which the maximum number of users are connected, a configuration table (18) comprising n locations, each location assigned to a slot period, the central control unit writing in each location communication control information, said table being addressed by the slot numbers generated by the scheduling means to read and make available, the communication control information, distribution buffer means (20) comprising at least a first and a second part, each part having n addressable locations, addressed by means of addressing means responsive to the communication control information provided by the configuration table during each slot period to cause each interface involved in the to be established communications during that slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot number generated by the scheduling means.
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公开(公告)号：DE3850881D1
公开(公告)日：1994-09-01
申请号：DE3850881
申请日：1988-10-28
Applicant: IBM
Inventor： CALVIGNAC JEAN , LIPS JEAN-PIERRE , MILLET JEAN-MARC , MUNIER JEAN-MARIE , NAUDIN BERNARD
IPC: G06F15/16 , G06F13/38 , G06F13/42 , G06F15/167 , G06F15/177
Abstract: The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. The messages are received by memory interface 22 from the source users and then are enqueued in link inbound queues (LIQ) which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface 22 sends a dequeue order request to the centralized control means, said request identifying the corresponding user queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface 22 sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by memory interface 22.
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