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公开(公告)号：BE787291A
公开(公告)日：1972-12-01
申请号：BE787291
申请日：1972-08-07
Applicant: IBM
Inventor： BEAUSOLEIL W F , PHELPS B E
Abstract: A hierarchical memory for a data processing system which is comprised of a number of different independent storage modules and a main memory backing store. Each data handling element of the system has an independent storage module associated with it as a dedicated buffer. A larger high speed main storage is used as a backing store. Each data handling element presumes that any data it needs is located in its dedicated buffer. If the data is not in the dedicated buffer, the data handling element scans all the other buffers until the desired data is located.
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公开(公告)号：BE785380A
公开(公告)日：1972-10-16
申请号：BE785380
申请日：1972-06-23
Applicant: IBM
Inventor： BEAUSOLEIL W F
Abstract: A computer memory, most particularly a monolithic memory, may be constructed of components which contain defective bit cells. During the production process, the monolithic chips are sorted into groups in accordance with the chip sector which contains one or more defective cells. The chips are then mounted on memory cards, with all of the chips having a defect in a given chip sector being mounted on a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The address wiring of the memory is provided in such a manner as to ensure that no given memory word, or defined group of bits within a memory word, contains within it more than one memory cell that is known or suspected to be defective. Means are also provided for deriving from the address of any given memory word the bit location within said word of a defective or suspicious bit. In one embodiment shown herein, the suspect bit is bypassed in favor of a redundant bit provided within the memory system. In another embodiment described herein, the suspect bit is utilized just as if it were a good bit, but, upon detection of an error, the suspect bit will be presumed to be in error.
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公开(公告)号：BE775348A
公开(公告)日：1972-03-16
申请号：BE775348
申请日：1971-11-16
Applicant: IBM
Inventor： BEAUSOLEIL W F , HO I T , PRICER W D
IPC: G06F12/08 , G11C11/415 , G11C19/00 , G11C
Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.
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公开(公告)号：BE759562A
公开(公告)日：1971-04-30
申请号：BE759562D
Applicant: IBM
Inventor： BEAUSOLEIL W F , ORDEMANN F A JR , PRICER W D , VOGL NORBERT G JR
Abstract: An electronic bulk storage having the characteristics of a sequential access storage device. Data are stored parallel by word in a plurality of electronically rotatable memory elements selectable by a memory selection matrix. Each element has a feed-back loop for recirculating data and when selected, a group of elements at an address N is read in parallel a word at a time by electronically rotating data bits stored in the selected memory elements at an address. Controls are provided to select memory elements N+1 whenever elements at address N are selected by the selection matrix. First data is read out of the elements at address N and then data is read out of the elements at address N+1 without any time lost for reselection of memory elements.
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Patent Agency Ranking
公开(公告)号：SE361369B
公开(公告)日：1973-10-29
申请号：SE1745470
申请日：1970-12-22
Applicant: IBM
Inventor： BEAUSOLEIL W F , ORDEMANN F A , PRICER W D , VOGL N G
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公开(公告)号：BE760238A
公开(公告)日：1971-05-17
申请号：BE760238
申请日：1970-12-11
Applicant: IBM
Inventor： BEAUSOLEIL W F
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公开(公告)号：SE384587B
公开(公告)日：1976-05-10
申请号：SE1017672
申请日：1972-08-04
Applicant: IBM
Inventor： BEAUSOLEIL W F , PHELPS B E
Abstract: A hierarchical memory for a data processing system which is comprised of a number of different independent storage modules and a main memory backing store. Each data handling element of the system has an independent storage module associated with it as a dedicated buffer. A larger high speed main storage is used as a backing store. Each data handling element presumes that any data it needs is located in its dedicated buffer. If the data is not in the dedicated buffer, the data handling element scans all the other buffers until the desired data is located.
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公开(公告)号：SE382516B
公开(公告)日：1976-02-02
申请号：SE210072
申请日：1972-02-22
Applicant: IBM
Inventor： BEAUSOLEIL W F , BROWN D T , WALKER E L
Abstract: This specification discloses a bubble domain memory in which data is arranged for immediacy of access in accordance with its last use. The memory comprises a plurality of parallel shift registers in which data can be accessed in parallel. In other words, each of the shift registers contains a bit of a page or word so that by the performance of one shifting operation all of the bits of the page or word can be accessed. Data in each shift register is arranged in its order of last use so that the access position K of a shift register having K bit positions contains the last bit of information used and the position K-1 preceding the access position K in the shift register contains the bit of data used just previously to the data in the access position K and so on. In these shift registers the shift positions are arranged in loops for shifting the data between the positions of the shift register. Two such loops are provided, one of the loops contains all the shift positions so that data in any position in the shift register can be shifted into the access position K of the register for reading or writing. The other loop contains all the positions of the shift register but the access position K. This second loop is for reordering the data in the shift register in order of last use after data has been shifted into the access position K for reading or writing by the first loop.
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