公开(公告)号：BE773703A

公开(公告)日：1972-01-31

申请号：BE773703

申请日：1971-10-08

Applicant: IBM

Inventor： BEAUSOLEIL W F ,  HO I T ,  JEN T-S ,  PRICER W D

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  H01L23/535 ,  H01L27/10 ,  G11C

公开(公告)号：SE384944B

公开(公告)日：1976-05-24

申请号：SE779672

申请日：1972-06-14

Applicant: IBM

Inventor： HO I T ,  YU H N ,  RISEMAN J

IPC: G11C16/04 ,  H01L27/105 ,  H01L29/10 ,  H01L29/423 ,  H01L29/768 ,  G11C11/24 ,  G11C11/34

公开(公告)号：SE391594B

公开(公告)日：1977-02-21

申请号：SE7307950

申请日：1973-06-06

Applicant: IBM

Inventor： HO I T ,  RISEMAN J

IPC: G06F12/08 ,  B23D45/00 ,  G06F13/00 ,  G11B20060101 ,  G11C7/00 ,  G11C11/00 ,  G11C11/40 ,  G11C9/06

公开(公告)号：SE384092B

公开(公告)日：1976-04-12

申请号：SE691372

申请日：1972-05-26

Applicant: IBM

Inventor： HO I T ,  JEN T-S

IPC: G11C8/10 ,  G11C11/414 ,  G11C11/415 ,  H03K3/35 ,  H03K17/00 ,  H03K17/62 ,  H03K17/73 ,  G11C7/00

公开(公告)号：BE775348A

公开(公告)日：1972-03-16

申请号：BE775348

申请日：1971-11-16

Applicant: IBM

Inventor： BEAUSOLEIL W F ,  HO I T ,  PRICER W D

IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00 ,  G11C

Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

公开(公告)号：SE383428B

公开(公告)日：1976-03-08

申请号：SE1502471

申请日：1971-11-24

Applicant: IBM

Inventor： BEAUSOLEIL W F ,  HO I T ,  JEN T-S ,  PRICER W D

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  H01L23/535 ,  H01L27/10 ,  G11C11/40

公开(公告)号：SE383427B

公开(公告)日：1976-03-08

申请号：SE1638071

申请日：1971-12-21

Applicant: IBM

Inventor： BEAUSOLEIL W F ,  HO I T ,  PRICER W D

IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00 ,  G11C9/06

Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.