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公开(公告)号：DE3786851D1
公开(公告)日：1993-09-09
申请号：DE3786851
申请日：1987-05-05
Applicant: IBM
IPC: H01L21/302 , C23F1/00 , G01N21/64 , H01J37/32 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/3213 , C23F4/00
Abstract: Laser induced fluorescence is utilized to detect the reactive ion etch-through of a given layer in a wafer by detecting a large change in the concentration of a wafer selected minor species from the wafer in the etching plasma. This selected minor species must be present in a significantly different concentration in the etched given layer compared to any of the other layers in the wafer in order to provide a proper endpoint detection. In one embodiment, when the large change in the selected minor species concentration is detected, then the RF electrodes for the reactor are de-energized.
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公开(公告)号：DE69500949T2
公开(公告)日：1998-05-28
申请号：DE69500949
申请日：1995-05-19
Applicant: IBM
Inventor： BENNETT REID STUART , SEK-ON YEE DENNIS
IPC: H01L21/3065 , H01L21/302 , H01L21/336 , H01L21/60 , H01L29/78
Abstract: Forming an LDD transistor in a Si layer comprises: (a) preparing a Si substrate; (b) forming a gate stack comprising a gate oxide, a gate electrode layer having a gate top surface and a first sacrificial dielectric; (c) patterning the gate stack to define a gate stack column having vertical sidewalls and source and drain regions in the Si layer adjoining the gate stack column; (d) oxidising the vertical sidewalls; (e) depositing a conformal etch resistant dielectric over the gate stack column and the source and drain areas; (f) depositing a second sacrificial dielectric over the conformal dielectric in the gate stack column and the source and drain areas; (g) directionally etching horizontal portions of the second sacrificial dielectric and the conformal dielectric, thereby exposing the first sacrificial dielectric and the source and drain areas and leaving first gate sidewalls including at least the conformal dielectric; (h) removing the first sacrificial dielectric, leaving vertical alignment stubs of the conformal dielectric adjacent extending from the first gate sidewalls above the gate top surface; (i) depositing a protective conformal dielectric having a nominal contact cover thickness above the gate stack column, thereby forming self-aligned protective members about each of the vertical alignment stubs and having a thickness greater than the nominal contact cover thickness; (j) depositing a first interlayer dielectric; (k) etching contact holes above the source and drain regions through the interlayer dielectric and through the protective conformal dielectric to the source and drain regions, whereby a residual thickness of the protective conformal dielectric remains above corners of the gate stack column; and (l) completing the IC.
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公开(公告)号：DE69500949D1
公开(公告)日：1997-12-04
申请号：DE69500949
申请日：1995-05-19
Applicant: IBM
Inventor： BENNETT REID STUART , SEK-ON YEE DENNIS
IPC: H01L21/3065 , H01L21/302 , H01L21/336 , H01L21/60 , H01L29/78
Abstract: Forming an LDD transistor in a Si layer comprises: (a) preparing a Si substrate; (b) forming a gate stack comprising a gate oxide, a gate electrode layer having a gate top surface and a first sacrificial dielectric; (c) patterning the gate stack to define a gate stack column having vertical sidewalls and source and drain regions in the Si layer adjoining the gate stack column; (d) oxidising the vertical sidewalls; (e) depositing a conformal etch resistant dielectric over the gate stack column and the source and drain areas; (f) depositing a second sacrificial dielectric over the conformal dielectric in the gate stack column and the source and drain areas; (g) directionally etching horizontal portions of the second sacrificial dielectric and the conformal dielectric, thereby exposing the first sacrificial dielectric and the source and drain areas and leaving first gate sidewalls including at least the conformal dielectric; (h) removing the first sacrificial dielectric, leaving vertical alignment stubs of the conformal dielectric adjacent extending from the first gate sidewalls above the gate top surface; (i) depositing a protective conformal dielectric having a nominal contact cover thickness above the gate stack column, thereby forming self-aligned protective members about each of the vertical alignment stubs and having a thickness greater than the nominal contact cover thickness; (j) depositing a first interlayer dielectric; (k) etching contact holes above the source and drain regions through the interlayer dielectric and through the protective conformal dielectric to the source and drain regions, whereby a residual thickness of the protective conformal dielectric remains above corners of the gate stack column; and (l) completing the IC.
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公开(公告)号：DE3786851T2
公开(公告)日：1994-03-17
申请号：DE3786851
申请日：1987-05-05
Applicant: IBM
IPC: H01L21/302 , C23F1/00 , G01N21/64 , H01J37/32 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/3213 , C23F4/00
Abstract: Laser induced fluorescence is utilized to detect the reactive ion etch-through of a given layer in a wafer by detecting a large change in the concentration of a wafer selected minor species from the wafer in the etching plasma. This selected minor species must be present in a significantly different concentration in the etched given layer compared to any of the other layers in the wafer in order to provide a proper endpoint detection. In one embodiment, when the large change in the selected minor species concentration is detected, then the RF electrodes for the reactor are de-energized.
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