中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.018 seconds)

    SPIN-UP FOR SMART DASD
    1.
    发明专利
    SPIN-UP FOR SMART DASD 失效

    公开(公告)号：JP2000010678A

    公开(公告)日：2000-01-14

    申请号：JP11431199

    申请日：1999-04-22

    Applicant: IBM

    Inventor： BERGLUND NEIL CLAIR ,  VERBURG DAVID ARVIN

    IPC: G06F1/26 ,  G11B19/00

    Abstract: PROBLEM TO BE SOLVED: To efficiently execute the spin-up of a disk drive (DASD) at high speed by calculating the maximum number of devices, which can be simultaneously activated, based on the determination concerning the required power condition of a system device and the power supply ability of a system and automatically controlling the activation of the electric system. SOLUTION: A system power control network(SPCN) microprocessor 101 respectively connects power units 102A and 102B, DASD 103A and 103B and disk drive input/output controllers(IOC) 104A and 104B. Concerning the power capacity of the respective power units 102A and 102B in the system and the power of system components such as DASD 103A and 103B and IOC 104A and 104B or the like, based on the determination of the required power condition and power supply ability of the system device, that microprocessor 101 calculates the maximum number of devices, which can be simultaneously activated, and automatically controls the activation of the electric system.

    Power fault analysis in a computer system
    3.
    发明专利
    Power fault analysis in a computer system 未知

    公开(公告)号：AU2002307936A1

    公开(公告)日：2002-12-23

    申请号：AU2002307936

    申请日：2002-05-10

    Applicant: IBM

    Inventor： TIETJEN JOHN NICOLAUS ,  BERGLUND NEIL CLAIR

    IPC: G06F1/30 ,  G06F1/28 ,  G06F11/34 ,  G06F11/28 ,  G06F11/14

    Abstract: A power fault diagnostic mechanism for a computer system having a power system that includes a controller. A variable is recorded in a non-volatile memory associated with the power system. The variable assumes a first state when the computer system is powered on and operating. The variable remains in the first state until it enters a second state when the computer system is powered off in response to a power-off request. The controller operates in a standby mode when the computer system is powered off. Upon being powered up, e.g., after a utility power disturbance, the controller reads the variable in the non-volatile memory. This allows determination of whether a disturbance has occurred, even when the computer system was powered off. The controller maintains a local error log based on the variable accessed from the non-volatile memory. A system error log is updated by the operating system using the local error log.

    DATA PROCESSING SYSTEM FOR INTERFACING A MAIN STORE WITH A CONTROL SECTRON AND A DATA PROCESSING SECTION
    6.
    发明专利
    DATA PROCESSING SYSTEM FOR INTERFACING A MAIN STORE WITH A CONTROL SECTRON AND A DATA PROCESSING SECTION 未知

    公开(公告)号：DE2965798D1

    公开(公告)日：1983-08-04

    申请号：DE2965798

    申请日：1979-09-24

    Applicant: IBM

    Inventor： BERGLUND NEIL CLAIR ,  LUICK DAVID ARNOLD

    IPC: G06F13/12 ,  G06F9/22 ,  G06F9/30 ,  G06F12/00 ,  G06F13/42 ,  G06F13/00 ,  G06F9/06

    Abstract: This invention relates to apparatus for interfacing a storage memory with a central processing unit. Improved efficiency in the operation of a computer system is achieved by interface logic that control the operating rate of a central processing unit 14 to be compatible with the slower operating rate of main memory 12. Microinstructions are decoded and interlock latches are generated to provide a main store interface holdoff signal that is applied to holdoff latch logic. Normally, the holdoff latch logic provides load control signals to sequence the operating cycle of the central processing unit. Under certain identified microinstruction conditions, an interlock latch is generated and the load control signals are not output from the holdoff logic, thereby inhibiting the sequencing operation of the central processing unit. Interlock latches that are generated includes a register-in-use interlock and an invalid data interlock from each register that is used to fetch data from and store data into main memory.

    7.
    发明专利
    未知

    公开(公告)号：DE3688277D1

    公开(公告)日：1993-05-19

    申请号：DE3688277

    申请日：1986-09-16

    Applicant: IBM

    Inventor： AAKRE DAVID ELGAR ,  ABRAHAMSON DOUGLAS JOHN ,  BERGLUND NEIL CLAIR ,  BETTERMANN VINCENT ALFRED ,  HEIM LLOYD STEPHEN ,  MOE KENNETH ARDELLE

    IPC: G06F13/14 ,  G06F12/06

    Abstract: An automatic address assignment system (10) has a plurality of I/O devices (20,22,...M,28,30,...P(14) coupled to a bus. Each device contains a unique machine-readable identifier which is used to select the device for address assignment. The identifier is a binary bit string. Each bit position in the bit string is selected by the host in a serial manner with the host specifying which binary value is being solicited. All devices whose identifier digit matches the solicited value respond positively and remain in contention for address assignment. The other devices will not respond and drop out of contention for address assignment until the sequence is restarted from the first bit. After the bit sequence is completed, the address for that device is bused to the device, and the sequence is restarted from the first bit until all devices have been assigned an address.

Patent Agency Ranking