公开(公告)号：DE2966069D1

公开(公告)日：1983-09-22

申请号：DE2966069

申请日：1979-09-24

Applicant: IBM

Inventor： BERGLUND NEIL CLAIR ,  CROWLEY RICHARD DOUGLAS ,  KEMPKE WILLIAM GEORGE ,  RICHARDSON WILLIAM CAIN

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/06 ,  G06F13/00

Abstract: An I-fetch control system for a computer includes a control store (30) for storing end op, I-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next @micro-instruction @ to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to I-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to I-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (30) to being E-phase.

公开(公告)号：DE2965034D1

公开(公告)日：1983-04-21

申请号：DE2965034

申请日：1979-07-25

Applicant: IBM

Inventor： BERGLUND NEIL CLAIR ,  KEMPKE WILLIAM GEORGE

IPC: G06F11/08 ,  G06F9/22 ,  G06F11/10 ,  G06F11/28 ,  G06F12/08 ,  G06F12/16 ,  G06F9/24

公开(公告)号：DE2702722A1

公开(公告)日：1977-08-11

申请号：DE2702722

申请日：1977-01-24

Applicant: IBM

Inventor： HOFFMAN ROY LOUIS ,  KEMPKE WILLIAM GEORGE ,  SOLTIS FRANK GERALD

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/455 ,  G06F9/20

Abstract: A special directly executable instruction, Fetch Instruction Operand Address (FIOA) is accessed in response to encountering a complex non-directly executable instruction. Execution of the FIOA instruction causes generation of control signals for address calculation of the operands in the non-directly executable instruction by the same I phase hardware used by other directly executable instructions.

公开(公告)号：DE2965935D1

公开(公告)日：1983-08-25

申请号：DE2965935

申请日：1979-09-24

Applicant: IBM

Inventor： BERGLUND NEIL CLAIR ,  KEMPKE WILLIAM GEORGE ,  RICHARDSON WILLIAM CAIN

IPC: G06F9/22 ,  G06F9/28 ,  G06F9/38

公开(公告)号：CH634936A5

公开(公告)日：1983-02-28

申请号：CH687178

申请日：1978-06-23

Applicant: IBM

Inventor： HOFFMAN ROY LOUIS ,  KEMPKE WILLIAM GEORGE ,  MCCULLOUGH JOHN WARREN ,  SOLTIS FRANK GERALD ,  TURNER RICHARD TAD

IPC: G06F9/46 ,  G06F9/48

公开(公告)号：DE2961891D1

公开(公告)日：1982-03-04

申请号：DE2961891

申请日：1979-09-24

Applicant: IBM

Inventor： MITCHELL GLEN ROBERT ,  KEMPKE WILLIAM GEORGE ,  JONES EUGENE REESE ,  HOUDEK MERLE EDWARD ,  RANWEILER JAMES GREGORY

IPC: G06F12/14 ,  G06F21/02 ,  G06F13/00

Abstract: Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction. Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.

公开(公告)号：IT7926080D0

公开(公告)日：1979-09-28

申请号：IT2608079

申请日：1979-09-28

Applicant: IBM

Inventor： MITCHELL GLEN ROBERT ,  KEMPKE WILLIAM GEORGE ,  JONES EUGENE REESE ,  HOUDEK MERLE EDWARD ,  RANWEILER JAMES GREGORY

IPC: G06F12/14 ,  G06F21/02 ,  G06F

Abstract: Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction. Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.

公开(公告)号：IT1165345B

公开(公告)日：1987-04-22

申请号：IT2608079

申请日：1979-09-28

Applicant: IBM

Inventor： MITCHELL GLEN ROBERT ,  KEMPKE WILLIAM GEORGE ,  JONES EUGENE REESE ,  HOUDEK MERLE EDWARD ,  RANWEILER JAMES GREGORY

IPC: G06F12/14 ,  G06F21/02 ,  G06F

Abstract: Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction. Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.

公开(公告)号：DE3069585D1

公开(公告)日：1984-12-13

申请号：DE3069585

申请日：1980-06-03

Applicant: IBM

Inventor： HOFFMAN ROY LOUIS ,  KEMPKE WILLIAM GEORGE ,  MCCULLOUGH JOHN WARREN ,  SOLTIS FRANK GERALD ,  TURNER RICHARD TAD

IPC: G06F9/46 ,  G06F9/48 ,  G06F3/04

Abstract: The specification concerns a task handling apparatus for a computer system where the task dispatcher is selectively operable under instruction control for performing task queue selection and where the intertask communication mechanism can return a task dispatching element (TDE) to a non-prime task dispatching queue (TDQ) as well as to the prime TDQ. Whenever a TDE is returned to the prime TDQ, the task dispatcher makes a pre-emptive task switch. Also, if there are no task dispatching elements on the current non-prime TDQ, the task dispatcher switches to dispatch TDE's from the prime TDQ.

公开(公告)号：AU3645078A

公开(公告)日：1979-11-29

申请号：AU3645078

申请日：1978-05-24

Applicant: IBM

Inventor： HOFFMAN ROY LOUIS ,  SOLTIS FRANK GERALD ,  TURNER RICHARD TAD ,  KEMPKE WILLIAM GEORGE ,  MCCULLOUGH JOHN WARREN

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/18

Abstract: Task handling apparatus in a computer system is structured to be common to system control tasks, user tasks and I/O tasks. Although the task handling apparatus contains a task priority structure, all tasks are handled in the same manner, and there are no fixed interrupt levels for I/O tasks. There are N levels of priority, and N is variable. Each task is a server for a functional request. Task dispatching elements (TDE's) are enqueued in priority sequence on a task dispatching queue (TDQ). A task dispatcher functions to dispatch the highest priority TDE on the TDQ, if any, and to perform task switching. Intertask communication is accomplished by send message, send count, receive message and receive count mechanisms, and is coupled with task synchronization. Task synchronization is achieved by dequeueing and enqueueing TDE's on the TDQ. An active task becomes inactive dispatchable when a higher priority TDE is enqueued on the TDQ by send message or send count mechanisms. The active task becomes inactive waiting when a receive message or receive count is not satisfied. An inactive dispatchable task becomes the active task when it becomes the highest priority enqueued TDE on the TDQ by the receive message or receive count mechanisms. An inactive waiting task becomes either the active task or an inactive dispatchable task after being enqueued on the TDQ by the send message or send count mechanisms, depending upon whether it is the highest or other than the highest priority TDE on the TDQ.