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公开(公告)号:GB2355327A
公开(公告)日:2001-04-18
申请号:GB0017095
申请日:2000-07-13
Applicant: IBM
Inventor: KIRIHATA TOSHIAKI , STORASKA DANIEL , NARAYAN CHANDRASEKHAR , TONTI WILLIAM , BERTIN CLAUDE , VAN HEEL NICK
IPC: G11C14/00 , G11C11/00 , G11C16/02 , G11C16/04 , G11C29/04 , H01L21/8246 , H01L27/112
Abstract: A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip. Each cell includes a capacitor which permanently stores a 1 by breakdown of the capacitor when the cell acts as an EPROM cell.
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公开(公告)号:GB2355327B
公开(公告)日:2004-02-18
申请号:GB0017095
申请日:2000-07-13
Applicant: IBM
Inventor: KIRIHATA TOSHIAKI , STORASKA DANIEL , NARAYAN CHANDRASEKHAR , TONTI WILLIAM , BERTIN CLAUDE , VAN HEEL NICK
IPC: G11C14/00 , G11C11/00 , G11C16/02 , G11C16/04 , G11C29/04 , H01L21/8246 , H01L27/112
Abstract: A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.
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