公开(公告)号：EP1388053A4

公开(公告)日：2008-04-16

申请号：EP01987447

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3885

Abstract: A method and apparatus for issuing and executing memory instructions so as to maximize the number of requests issued to a highly pipelined memory and avoid reading data from memory (10) before a corresponding write to memory (10). The memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：JP2002342161A

公开(公告)日：2002-11-29

申请号：JP2002132962

申请日：2002-05-08

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  EKANADHAM KATTAMURI ,  PATTNAIK PRATAP CHANDRA

IPC: G06F12/08 ,  G11C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a memory structure and a method for processing a memory request from processor and returning a response from the various levels of the memory structure to a processor. SOLUTION: The memory levels L1 to LN of a memory structure 10 are mutually connected by a forward path 5 and a return path 7. The return path has a bandwidth being twice that of the forward path. How many responses are sent from each of the memory levels on the return path to the processor is decided by using an algorithm. The algorithm guarantees a constant bound on the rate of responses sent to the processor. Move specifically, if a write request is at the same level which it is targeted, or if a request at a memory level is targeted to a higher memory level, a controller at the memory level on the return path sends two responses to the processor. Otherwise, only one response is sent from the memory level on the return path.

公开(公告)号：CA2447425A1

公开(公告)日：2002-11-21

申请号：CA2447425

申请日：2001-12-21

Applicant: IBM

Inventor： EKANADHAM KATTAMURI ,  BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions so as t o maximize the number of requests issued to a highly pipelined memory and avoi d reading data from memory (10) before a corresponding write to memory (10). T he memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that i s targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：HU0400049A2

公开(公告)日：2004-04-28

申请号：HU0400049

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  EKANADHAM KATTAMURI ,  PATTNAIK PRATAP CHANDRA

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：CZ20032948A3

公开(公告)日：2004-01-14

申请号：CZ20032948

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：CA2376331A1

公开(公告)日：2002-11-11

申请号：CA2376331

申请日：2002-03-12

Applicant: IBM

Inventor： EKANADHAM KATTAMURI ,  PATTNAIK PRATAP C ,  BILARDI GIANFRANCO

IPC: G06F12/08 ,  G11C7/10 ,  G06F13/14 ,  G06F12/00

Abstract: A memory structure and method for handling memory requests from a processor and for returning correspondence responses to the processor from various levels of t he memory structure. The memory levels of the memory structure are interconnected by a forward an d return path with the return path having twice the bandwidth of the forward path. An algorithm is used to determine how many responses are sent from each memory level on the return path to the processor. This algorithm is designed to guarantee a constant bound on the rate of responses sent to the processor. More specifically, if a write request is at the same level to which it is targeted, or if a request at a memory level is targeted to a higher memory level, then two responses are forwarded from a controller at the memory level on the return path to the processor. Otherwise, only one response is forwarded from the memory level on the return path.

公开(公告)号：CA2447425C

公开(公告)日：2008-09-09

申请号：CA2447425

申请日：2001-12-21

Applicant: IBM

Inventor： PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI ,  BILARDI GIANFRANCO

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions so as t o maximize the number of requests issued to a highly pipelined memory and avoi d reading data from memory (10) before a corresponding write to memory (10). T he memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that i s targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：PL364643A1

公开(公告)日：2004-12-13

申请号：PL36464301

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.