公开(公告)号：EP1388053A4

公开(公告)日：2008-04-16

申请号：EP01987447

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3885

Abstract: A method and apparatus for issuing and executing memory instructions so as to maximize the number of requests issued to a highly pipelined memory and avoid reading data from memory (10) before a corresponding write to memory (10). The memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：JP2002342161A

公开(公告)日：2002-11-29

申请号：JP2002132962

申请日：2002-05-08

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  EKANADHAM KATTAMURI ,  PATTNAIK PRATAP CHANDRA

IPC: G06F12/08 ,  G11C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a memory structure and a method for processing a memory request from processor and returning a response from the various levels of the memory structure to a processor. SOLUTION: The memory levels L1 to LN of a memory structure 10 are mutually connected by a forward path 5 and a return path 7. The return path has a bandwidth being twice that of the forward path. How many responses are sent from each of the memory levels on the return path to the processor is decided by using an algorithm. The algorithm guarantees a constant bound on the rate of responses sent to the processor. Move specifically, if a write request is at the same level which it is targeted, or if a request at a memory level is targeted to a higher memory level, a controller at the memory level on the return path sends two responses to the processor. Otherwise, only one response is sent from the memory level on the return path.

公开(公告)号：HU0400049A2

公开(公告)日：2004-04-28

申请号：HU0400049

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  EKANADHAM KATTAMURI ,  PATTNAIK PRATAP CHANDRA

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：DE112015005602T5

公开(公告)日：2017-09-07

申请号：DE112015005602

申请日：2015-12-11

Applicant: IBM

Inventor： HALL WILLIAM ERIC ,  BOIVIE RICHARD HAROLD ,  HUNT GUERNEY ,  PENDARAKIS DIMITRIOS ,  SAFFORD DAVID ROBERT ,  EKANADHAM KATTAMURI ,  KAPUR MOHIT ,  GOLDMAN KENNETH ALAN ,  JAIN BHUSHAN PRADIP ,  VALDEZ ENRIQUILLO ,  SANDON PETER ANTHONY

IPC: G06F12/14

Abstract: Ein Prozessor in einem Computersystem, wobei der Prozessor einen Mechanismus enthält, der ein sicheres Objekt unterstützt, das Daten beinhaltet, die geschützt werden, so dass andere Software in dem Computersystem auf diese Daten nicht zugreifen oder diese unbemerkt verfälschen kann, wodurch sowohl Vertraulichkeit als auch Integrität der Daten des sicheren Objekts geschützt werden, während die Daten des sicheren Objekts dem sicheren Objekt selbst während des Ausführens des sicheren Objekts zur Verfügung gestellt werden. Dieser Mechanismus enthält einen Krypto-Mechanismus, der Daten des sicheren Objekts entschlüsselt und daran Integritätsprüfungen ausführt, wenn die Daten des sicheren Objekts von einem externen Speichersystem in das Computersystem verschoben werden, und einen Integritätswert der Daten des sicheren Objekts verschlüsselt und aktualisiert, wenn die Daten des sicheren Objekts aus dem Computersystem zu dem externen Speichersystem verschoben werden, und einen Speicherschutzmechanismus, der die Vertraulichkeit und Integrität von Daten des sicheren Objekts schützt, wenn sich diese Daten in dem Speicher des Computersystems befinden.

公开(公告)号：CA2447425A1

公开(公告)日：2002-11-21

申请号：CA2447425

申请日：2001-12-21

Applicant: IBM

Inventor： EKANADHAM KATTAMURI ,  BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions so as t o maximize the number of requests issued to a highly pipelined memory and avoi d reading data from memory (10) before a corresponding write to memory (10). T he memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that i s targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：GB2318660A

公开(公告)日：1998-04-29

申请号：GB9719580

申请日：1997-09-16

Applicant: IBM

Inventor： RECHTSCHAFFEN RUDOLPH NATHAN ,  EKANADHAM KATTAMURI

IPC: G06F9/38 ,  G06F9/45 ,  G06F15/80 ,  G06F9/44

Abstract: A self-parallelising computer system is described in which a single execution sequence of instructions is partitioned at run-time into a set of instruction subsequences, each instruction subsequence being executed on a different one of a set of separate processing elements 100 that share a common register file 160. The processing elements rename the registers used by the instructions that modify registers so that when the instructions are executed in parallel mode the result of the executions will appear in the common set of registers accessible to all the processing elements. Each instruction within the sequential execution sequence that modifies a register gets assigned the next higher number hardware register from the common register pool. The architected register modified in this instruction is now renamed to this hardware register and so identified within a register correspondence table 180 Conceptually subsequent instructions that require this register as input will now be associated with the renamed common register and derive their input from the result of the execution of the register-modifying instruction. As such there is no need for sending and receiving obligations to resolve register set/use requirements implied by the sequential execution sequence.

公开(公告)号：CZ20032948A3

公开(公告)日：2004-01-14

申请号：CZ20032948

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：CA2376331A1

公开(公告)日：2002-11-11

申请号：CA2376331

申请日：2002-03-12

Applicant: IBM

Inventor： EKANADHAM KATTAMURI ,  PATTNAIK PRATAP C ,  BILARDI GIANFRANCO

IPC: G06F12/08 ,  G11C7/10 ,  G06F13/14 ,  G06F12/00

Abstract: A memory structure and method for handling memory requests from a processor and for returning correspondence responses to the processor from various levels of t he memory structure. The memory levels of the memory structure are interconnected by a forward an d return path with the return path having twice the bandwidth of the forward path. An algorithm is used to determine how many responses are sent from each memory level on the return path to the processor. This algorithm is designed to guarantee a constant bound on the rate of responses sent to the processor. More specifically, if a write request is at the same level to which it is targeted, or if a request at a memory level is targeted to a higher memory level, then two responses are forwarded from a controller at the memory level on the return path to the processor. Otherwise, only one response is forwarded from the memory level on the return path.

公开(公告)号：DE112015005602B4

公开(公告)日：2024-09-26

申请号：DE112015005602

申请日：2015-12-11

Applicant: IBM

Inventor： BOIVIE RICHARD HAROLD ,  HALL WILLIAM ERIC ,  HUNT GUERNEY ,  PENDARAKIS DIMITRIOS ,  SAFFORD DAVID ROBERT ,  EKANADHAM KATTAMURI ,  KAPUR MOHIT ,  GOLDMAN KENNETH ALAN ,  JAIN BHUSHAN PRADIP ,  VALDEZ ENRIQUILLO ,  SANDON PETER ANTHONY

IPC: G06F12/14 ,  G06F21/53

Abstract: Verfahren zum Schützen von Vertraulichkeit und Integrität eines sicheren Objekts, das in einem Computersystem ausgeführt wird, durch Schützen der Speicherseiten, die Eigentum des sicheren Objekts sind, durch folgende Schritte:Zuweisen einer Kennung zu einem sicheren Objekt, wobei die Kennung für jedes sichere Objekt eindeutig ist;Bezeichnen der Speicherseiten, die Eigentum eines sicheren Objekts sind, mit der Kennung des sicheren Objekts;Führen einer Tabelle der Überwachungseinrichtung für Zugangssteuerung (ACM) für die Speicherseiten in dem System;Steuern des Zugriffs auf Speicherseiten durch Überwachen von Lade- und Speicherbefehlen und Vergleichen von Daten in der ACM-Tabelle mit der Kennung der Software, die diese Befehle ausführt; undBeschränken des Zugriffs auf eine Speicherseite auf den Eigentümer der Speicherseite;Verwenden von sicheren Objekten in einem Computersystem zum Schützen von virtuellen Maschinen in einem System, das ein gleichzeitiges Ausführen mehrerer virtueller Maschinen unterstützt, so dass Daten in einer virtuellen Maschine geschützt sind, so dass andere Software in dem Computersystem auf diese Daten nicht zugreifen oder diese unbemerkt verfälschen kann, wodurch sowohl Vertraulichkeit als auch Integrität der virtuellen Maschine geschützt sind, während die Daten in der virtuellen Maschine der virtuellen Maschine selbst während des Ausführens der virtuellen Maschine zur Verfügung gestellt werden;Bilden eines sicheren Objekts aus dem Abbild einer virtuellen Maschine; undAusführen des sicheren Objekts in einem System, das das Ausführen von sicheren Objekten unterstützt.

公开(公告)号：CA2447425C

公开(公告)日：2008-09-09

申请号：CA2447425

申请日：2001-12-21

Applicant: IBM

Inventor： PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI ,  BILARDI GIANFRANCO

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions so as t o maximize the number of requests issued to a highly pipelined memory and avoi d reading data from memory (10) before a corresponding write to memory (10). T he memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that i s targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.