公开(公告)号：EP1388053A4

公开(公告)日：2008-04-16

申请号：EP01987447

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3885

Abstract: A method and apparatus for issuing and executing memory instructions so as to maximize the number of requests issued to a highly pipelined memory and avoid reading data from memory (10) before a corresponding write to memory (10). The memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：JP2000148518A

公开(公告)日：2000-05-30

申请号：JP14120899

申请日：1999-05-21

Applicant: IBM

Inventor： FRANKE HUBERTUS ,  PATTNAIK PRATAP CHANDRA ,  KRIEGER ORRAN YAKOV ,  BARANSKY YURIJ ANDRIJ

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/50

Abstract: PROBLEM TO BE SOLVED: To permit improved scheduling based upon cache affinity by deciding the affinity of a thread by using the cache fit print of the thread and scheduling the execution of the thread for execution according to the affinity. SOLUTION: A cache monitor unit CMU 20 expands standard cache architecture. The CMU 20 monitors the right of proprietary rights and usage of the cache so as to measure the cache fit print of a calculation unit (process, thread). When current threads executing an instruction stream on a CPU 22 accesses the contents of a memory, the CPU 22 issues their requests to the cache 21. The affinity of threads regarding respective processors is decided by using the measured cache fit print. The execution of the threads by the processors is scheduled according to the affinity.

公开(公告)号：JP2002342161A

公开(公告)日：2002-11-29

申请号：JP2002132962

申请日：2002-05-08

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  EKANADHAM KATTAMURI ,  PATTNAIK PRATAP CHANDRA

IPC: G06F12/08 ,  G11C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a memory structure and a method for processing a memory request from processor and returning a response from the various levels of the memory structure to a processor. SOLUTION: The memory levels L1 to LN of a memory structure 10 are mutually connected by a forward path 5 and a return path 7. The return path has a bandwidth being twice that of the forward path. How many responses are sent from each of the memory levels on the return path to the processor is decided by using an algorithm. The algorithm guarantees a constant bound on the rate of responses sent to the processor. Move specifically, if a write request is at the same level which it is targeted, or if a request at a memory level is targeted to a higher memory level, a controller at the memory level on the return path sends two responses to the processor. Otherwise, only one response is sent from the memory level on the return path.

公开(公告)号：WO2006007043A2

公开(公告)日：2006-01-19

申请号：PCT/US2005015493

申请日：2005-05-04

Applicant: IBM

Inventor： JANN JOEFON ,  PATTNAIK PRATAP CHANDRA ,  BURUGULA RMANJANEYA SARMA

IPC: G06F12/00

CPC classification number: G06F12/127 ,  G06F12/023

Abstract: A method, information processing system, and computer readable medium for efficiently distributing a computer system's main memory among applications running in that operating system instance. More specifically, threshold values used by a page replacement algorithm of the virtual memory manager are automatically tuned in response to the load on the memory of a computer system. One such threshold value is the lower threshold of free memory which is changed as a function of the load on the memory. For example, such a load might be represented as the number of threads that were added to a waiting queue during a defined interval of time divided by the number of clock tics in that interval. This representation is known as the thread wait rate. This rate is then compared to a target rate to determine if the lower threshold value should be changed. When the free memory space falls below the lower threshold, a page replacement daemon is used to page out memory to make more memory space available.

Abstract translation: 一种用于在运行在该操作系统实例中的应用程序之间有效地分发计算机系统的主存储器的方法，信息处理系统和计算机可读介质。 更具体地，响应于计算机系统的存储器上的负载，自动调整由虚拟存储器管理器的页面替换算法使用的阈值。 一个这样的阈值是随着存储器上的负载而变化的空闲存储器的下限阈值。 例如，这样的负载可以表示为在定义的时间间隔内被添加到等待队列中的线程数除以该间隔中的时钟提示数。 该表示被称为线程等待速率。 然后将该速率与目标速率进行比较，以确定是否应该改变较低的阈值。 当可用内存空间低于下限阈值时，页面替换守护程序用于页面输出内存以使更多的内存空间可用。

公开(公告)号：CA2447425A1

公开(公告)日：2002-11-21

申请号：CA2447425

申请日：2001-12-21

Applicant: IBM

Inventor： EKANADHAM KATTAMURI ,  BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions so as t o maximize the number of requests issued to a highly pipelined memory and avoi d reading data from memory (10) before a corresponding write to memory (10). T he memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that i s targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：HU0400049A2

公开(公告)日：2004-04-28

申请号：HU0400049

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  EKANADHAM KATTAMURI ,  PATTNAIK PRATAP CHANDRA

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：CZ20032948A3

公开(公告)日：2004-01-14

申请号：CZ20032948

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：DE112016000915T5

公开(公告)日：2017-11-23

申请号：DE112016000915

申请日：2016-03-23

Applicant: IBM

Inventor： LI CHUNG-SHENG ,  HOGSTROM MATT RICHARD ,  BRECH BRAD ,  RATNAPARKHI RADHA ,  FRANKE HUBERTUS ,  PATTNAIK PRATAP CHANDRA ,  WILLIAMS MICHAEL DAVID ,  CROWDER SCOTT ,  HALIM NAGUI ,  PENDARAKIS DIMITRIOS ,  RAO JOSYULA

IPC: G06F21/00

Abstract: Bereitgestellt werden ein Verfahren und ein System, das ein Erstellen eines Sicherheitscontainers, der eine Workload und eine der Workload entsprechende Gruppe von Ressourcen beschreibt, in einer softwaredefinierten Umgebung, Festlegen einer Gruppe von Sicherheitskriterien für den Sicherheitscontainer, Überwachen der Workloads und der Gruppe von Ressourcen zumindest teilweise auf Grundlage der Gruppe von Sicherheitskriterien auf Sicherheitsereignisse hin und Anpassen eines oder mehrerer Sicherheitsmechanismen in Antwort auf ein Erkennen eines Sicherheitsereignisses beinhaltet.

公开(公告)号：CA2447425C

公开(公告)日：2008-09-09

申请号：CA2447425

申请日：2001-12-21

Applicant: IBM

Inventor： PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI ,  BILARDI GIANFRANCO

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions so as t o maximize the number of requests issued to a highly pipelined memory and avoi d reading data from memory (10) before a corresponding write to memory (10). T he memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that i s targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：PL364643A1

公开(公告)日：2004-12-13

申请号：PL36464301

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.