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    Method for forming improved self-assembled pattern of block copolymer
    3.
    发明专利
    Method for forming improved self-assembled pattern of block copolymer 有权
    用于形成改进的嵌段共聚物自组装图案的方法

    公开(公告)号：JP2007208255A

    公开(公告)日：2007-08-16

    申请号：JP2007008935

    申请日：2007-01-18

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： RUIZ RICARDO ,  ROBERT L SANDSTROM ,  BLACK CHARLES THOMAS

    IPC: H01L51/40 ,  H01L21/312 ,  H01L51/05 ,  H01L51/30

    CPC classification number: B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00 ,  Y10S430/146 ,  Y10T428/24479 ,  Y10T428/24488 ,  Y10T428/2457 ,  Y10T428/2462

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a self-assembled pattern on a surface of a substrate. SOLUTION: First, a block copolymer layer, which comprises a block copolymer having two or more immiscible polymeric block components, is applied onto a substrate that comprises a substrate surface with a trench therein. The trench specifically includes at least one narrow region flanked by two wide regions, and wherein the trench has a width variation of more than 50%. Annealing is subsequently carried out to effectuate phase separation between the two or more immiscible polymeric block components in the block copolymer layer, thereby forming periodic patterns that are defined by repeating structural units. Specifically, the periodic patterns at the narrow region of the trench are aligned in a predetermined direction and are essentially free of defects. Block copolymer films formed by the above-described method as well as semiconductor structures comprising such block copolymer films are also provided. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种在基板的表面上形成自组装图案的方法。 解决方案：首先，将包含具有两个或更多个不混溶的聚合物嵌段组分的嵌段共聚物的嵌段共聚物层施加到包含其中具有沟槽的衬底表面的衬底上。 沟槽具体包括至少一个两个宽的区域的窄区域，并且其中沟槽具有大于50％的宽度变化。 随后进行退火以实现嵌段共聚物层中的两种或更多种不混溶的聚合物嵌段组分之间的相分离，从而形成由重复结构单元定义的周期性图案。 具体地说，在沟槽的窄区域的周期性图案在预定方向上排列，并且基本上没有缺陷。 还提供了通过上述方法形成的嵌段共聚物膜以及包含这种嵌段共聚物膜的半导体结构。 版权所有（C）2007，JPO＆INPIT

    Ferroelectric memory transistor with resistively coupled floating gate
    4.
    发明专利
    Ferroelectric memory transistor with resistively coupled floating gate 未知

    公开(公告)号：SG71152A1

    公开(公告)日：2000-03-21

    申请号：SG1998003606

    申请日：1998-09-11

    Applicant: IBM

    Inventor： BLACK CHARLES THOMAS ,  WELSER JEFFREY JOHN

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

    Abstract: The present invention proposes a new type of single-transistor memory device, which stores information using the polarization of a ferroelectric material. The device is a floating-gate FET, with a ferroelectric material positioned between the gate and the floating gate, and a resistance, preferably in the form of a thin SiO2 dielectric between the floating gate and the transistor channel. Unlike previous designs, in this device the floating gate is both capacitively and resistively coupled to the transistor channel, which enables the device to be both read and written using low voltages. This device offers significant advantages for operation at low voltages and at high speeds, for repeated cycling of over 1010 times, since device durability is limited by the ferroelectric endurance rather than oxide breakdown, and for integration at gigabit densities.

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