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    2.
    发明专利
    未知

    公开(公告)号：DE69627086T2

    公开(公告)日：2004-02-26

    申请号：DE69627086

    申请日：1996-08-19

    Applicant: IBM

    Inventor： AGAHI FARID ,  PEZESHKI BARDIA ,  KASH JEFFREY ALAN ,  WELSER JEFFREY JOHN

    IPC: G02B6/00 ,  G02B6/12 ,  G02F1/313 ,  H01L31/0232 ,  H01L31/10 ,  G02B6/293

    Abstract: This invention describes how commercial silicon-on-insulator material can be used to fabricate both wavelength filters and wavelength-selective photodetectors. The silicon-on-insulator substrates (100) have a buried silicon dioxide layer (102) and a thin top silicon layer (104) and are manufactured for high speed electronics applications. However, in this invention, the thin silicon layer (104) is used as the core of a waveguide and the buried silicon dioxide (102) as a lower cladding region. Another cladding layer (106) and a low index waveguide (108) is fabricated on the commercial substrate to form an asymmetric waveguide coupler structure. The added low index waveguide (108) and the original thin silicon layer (104) form the two waveguides of the coupler. Since the two waveguide materials have very different indices of refraction, they are only phase-matched at one wavelength (111). Thus for a given thickness of materials, only one wavelength (111) couples between the two waveguides (104, 108). By adding an absorptive layer in the silicon waveguide and electrical contacts, wavelength sensitive photodetection is obtained. The buried insulator layer (102) is the key to device operation, providing a very low index buried cladding region.

    3.
    发明专利
    未知

    公开(公告)号：DE69627086D1

    公开(公告)日：2003-05-08

    申请号：DE69627086

    申请日：1996-08-19

    Applicant: IBM

    Inventor： AGAHI FARID ,  PEZESHKI BARDIA ,  KASH JEFFREY ALAN ,  WELSER JEFFREY JOHN

    IPC: G02B6/00 ,  G02B6/12 ,  G02F1/313 ,  H01L31/0232 ,  H01L31/10 ,  G02B6/293

    Abstract: This invention describes how commercial silicon-on-insulator material can be used to fabricate both wavelength filters and wavelength-selective photodetectors. The silicon-on-insulator substrates (100) have a buried silicon dioxide layer (102) and a thin top silicon layer (104) and are manufactured for high speed electronics applications. However, in this invention, the thin silicon layer (104) is used as the core of a waveguide and the buried silicon dioxide (102) as a lower cladding region. Another cladding layer (106) and a low index waveguide (108) is fabricated on the commercial substrate to form an asymmetric waveguide coupler structure. The added low index waveguide (108) and the original thin silicon layer (104) form the two waveguides of the coupler. Since the two waveguide materials have very different indices of refraction, they are only phase-matched at one wavelength (111). Thus for a given thickness of materials, only one wavelength (111) couples between the two waveguides (104, 108). By adding an absorptive layer in the silicon waveguide and electrical contacts, wavelength sensitive photodetection is obtained. The buried insulator layer (102) is the key to device operation, providing a very low index buried cladding region.

    Ferroelectric memory transistor with resistively coupled floating gate
    5.
    发明专利
    Ferroelectric memory transistor with resistively coupled floating gate 未知

    公开(公告)号：SG71152A1

    公开(公告)日：2000-03-21

    申请号：SG1998003606

    申请日：1998-09-11

    Applicant: IBM

    Inventor： BLACK CHARLES THOMAS ,  WELSER JEFFREY JOHN

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

    Abstract: The present invention proposes a new type of single-transistor memory device, which stores information using the polarization of a ferroelectric material. The device is a floating-gate FET, with a ferroelectric material positioned between the gate and the floating gate, and a resistance, preferably in the form of a thin SiO2 dielectric between the floating gate and the transistor channel. Unlike previous designs, in this device the floating gate is both capacitively and resistively coupled to the transistor channel, which enables the device to be both read and written using low voltages. This device offers significant advantages for operation at low voltages and at high speeds, for repeated cycling of over 1010 times, since device durability is limited by the ferroelectric endurance rather than oxide breakdown, and for integration at gigabit densities.

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