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公开(公告)号：CA2166369A1
公开(公告)日：1997-06-30
申请号：CA2166369
申请日：1995-12-29
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT JAMES
IPC: G06F9/45
Abstract: A system and method for determining alias information at the intercompilation unit level of a compilation process includes the steps of determining antialias sets from the alias information provided by the first stage of the compilation process, calculating pessimistic inter-compilation unit alias sets and refining these sets, after transitive closure as appropriate, with the anti-alias sets.
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公开(公告)号：GB2509653B
公开(公告)日：2015-12-09
申请号：GB201406775
申请日：2012-10-01
Applicant: IBM
Inventor： BLAINEY ROBERT JAMES , GSCHWIND MICHAEL KARL , MCINNES JAMES LAWRENCE , MUNROE STEVEN JAY , MEISSNER MICHAEL
IPC: G06F9/45
Abstract: A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
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公开(公告)号：CA2288614A1
公开(公告)日：2001-05-08
申请号：CA2288614
申请日：1999-11-08
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT JAMES , ARCHAMBAULT ROCH GEORGES
IPC: G06F9/45
Abstract: Loop allocation for optimizing compilers includes the generation of a progra m dependence graph for a source code segment. Control dependence graph representations of the nested loops, from innermost to outermost, are generated and data dependence graph representations are generated for each level of nested loop as constrained by the control dependence graph. An interference graph is generated with the nodes of the data dependence graph. Weights are generated for the edges of the interference graph reflecting the affinity between statements represented by the nodes joined by the edges. Nodes in the interference graph are given weights reflecting resource usage by the statements associated with the nodes. The interference graph is partitioned using a profitability test based on the weights of edges and nodes and on a correctness test based on the reachability of nodes in the data dependence graph. Code is emitted based on the partitioned interference graph.
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公开(公告)号：CA2166253A1
公开(公告)日：1997-06-29
申请号：CA2166253
申请日：1995-12-28
Applicant: IBM CANADA
IPC: G06F9/45
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公开(公告)号：CA2166252A1
公开(公告)日：1997-06-29
申请号：CA2166252
申请日：1995-12-28
Applicant: IBM CANADA
IPC: G06F9/45
Abstract: An interprocedural compilation method for aggregating global data variables in external storage to maximize data locality. Using the information displayed in a weighted interference graph in which node weights represent the size of data stored in each global variable and edges between variables represent access relationships between the globals, the global variables can be mapped into aggregates based on this frequency of access, while preventing the cumulative data size in any aggregate from exceeding a memory size restriction.
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Patent Agency Ranking
公开(公告)号：GB2509438B
公开(公告)日：2015-09-09
申请号：GB201405930
申请日：2012-09-14
Applicant: IBM
Abstract: Generating decode time instruction optimization (DTIO) object code that enables a DTIO enabled processor to optimize execution of DTIO instructions. A code sequence configured to facilitate DTIO in a DTIO enabled processor is identified by a computer. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A schedule associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified schedule that is configured to place the first instruction next to the second instruction. An object file is generated based on the modified schedule. The object file includes the first instruction placed next to the second instruction. The object file is emitted.
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公开(公告)号：GB2509438A
公开(公告)日：2014-07-02
申请号：GB201405930
申请日：2012-09-14
Applicant: IBM
Abstract: Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including an access to a variable at an offset outside of a location in a variable address reference table. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A scheduler cost function associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified scheduler cost function that is configured to place the first instruction next to the second instruction. An object file is generated responsive to the modified scheduler cost function. The object file includes the first instruction placed next to the second instruction. The object file is emitted.
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公开(公告)号：CA2288614C
公开(公告)日：2004-05-11
申请号：CA2288614
申请日：1999-11-08
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT JAMES , ARCHAMBAULT ROCH GEORGES
IPC: G06F9/45
Abstract: Loop allocation for optimizing compilers includes the generation of a progra m dependence graph for a source code segment. Control dependence graph representations of the nested loops, from innermost to outermost, are generated and data dependence graph representations are generated for each level of nested loop as constrained by the control dependence graph. An interference graph is generated with the nodes of the data dependence graph. Weights are generated for the edges of the interference graph reflecting the affinity between statements represented by the nodes joined by the edges. Nodes in the interference graph are given weights reflecting resource usage by the statements associated with the nodes. The interference graph is partitioned using a profitability test based on the weights of edges and nodes and on a correctness test based on the reachability of nodes in the data dependence graph. Code is emitted based on the partitioned interference graph.
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公开(公告)号：CA2166254A1
公开(公告)日：1997-06-29
申请号：CA2166254
申请日：1995-12-28
Applicant: IBM CANADA
IPC: G06F9/45
Abstract: A technique used during interprocedural compilation in which program objects are grouped together based on the weights of the connections between the objects and their costs. System-imposed constraints on memory size can be taken into account to avoid creating groupings that overload the system's capacity. The groupings can be distributed over memories located on different processors.
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10.发明专利
公开(公告)号：GB2509653A8
公开(公告)日：2015-11-11
申请号：GB201406775
申请日：2012-10-01
Applicant: IBM
Inventor： BLAINEY ROBERT JAMES , GSCHWIND MICHAEL KARL , MCINNES JAMES LAWRENCE , MUNROE STEVEN JAY , MEISSNER MICHAEL
IPC: G06F9/45
Abstract: A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
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