SELECTIVE DELAYING OF WRITE REQUESTS IN HARDWARE TRANSACTIONAL MEMORY SYSTEMS
    1.
    发明申请
    SELECTIVE DELAYING OF WRITE REQUESTS IN HARDWARE TRANSACTIONAL MEMORY SYSTEMS 审中-公开
    硬件事务存储器系统中写请求的选择性延迟

    公开(公告)号:WO2014039701A2

    公开(公告)日:2014-03-13

    申请号:PCT/US2013058298

    申请日:2013-09-05

    Applicant: IBM

    CPC classification number: G06F9/467

    Abstract: Techniques for conflict detection in hardware transactional memory (HTM) are provided. In one aspect, a method for detecting conflicts in HTM includes the following steps. Conflict detection is performed eagerly by setting read and write bits in a cache as transactions having read and write requests are made. A given one of the transactions is stalled when a conflict is detected whereby more than one of the transactions are accessing data in the cache in a conflicting way. An address of the conflicting data is placed in a predictor. The predictor is queried whenever the write requests are made to determine whether they correspond to entries in the predictor. A copy of the data corresponding to entries in the predictor is placed in a store buffer. The write bits in the cache are set and the copy of the data in the store buffer is merged in at transaction commit.

    Abstract translation: 提供硬件事务内存(HTM)冲突检测技术。 在一个方面,一种用于检测HTM中的冲突的方法包括以下步骤。 作为具有读取和写入请求的事务,通过在高速缓存中设置读取和写入位来热切地执行冲突检测。 当检测到冲突时,给定的一个事务处于停滞状态,即有多个事务以冲突的方式访问缓存中的数据。 冲突数据的地址放置在预测器中。 每当发出写入请求以确定它们是否对应于预测变量中的条目时,都会查询预测变量。 与预测变量中的条目相对应的数据的副本被放置在存储缓冲区中。 缓存中的写入位被设置,并且在事务提交时合并存储缓冲区中的数据副本。

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