公开(公告)号：DE2937777A1

公开(公告)日：1981-03-26

申请号：DE2937777

申请日：1979-09-19

Applicant: IBM DEUTSCHLAND

Inventor： BAZLEN DIETER DIPL ING DR ,  BOCK DIETRICH DIPL ING ,  GETZLAFF KLAUS J ING GRAD ,  HAJDU JOHANN ING GRAD ,  PAINKE HELMUT DIPL ING

IPC: G06F9/48 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/46

Abstract: In executing and controlling internal data flow for a particular program, it is often necessary to delay execution of an instruction by the insertion of an appropriate number of wait cycles. Thus, it may be necessary to interrupt instruction execution, for example, to insert a given number of wait cycles for channel access to common storage of the data processing system, for reloading a data or instruction buffer, or for a like situation. In such cases, the control unit has to ignore the particular instruction awaiting execution and execute another forced operation instead. An appropriate code is provided for a NO OPERATION instruction, say all bits zero. When a forced operation is to be executed, this code can be generated with fewer logic means at the output of the instruction register. As a result, there are no control signals active at the output of the decoder. The signals indicating forced operations have to be considered by the decoder only if a control signal is to be generated. If the control signals need be grouped for physical reasons, it is possible to determine which of these signals are a function of forced operations. This will negate the need to otherwise distribute these control signals throughout the decoder, thereby reducing and simplifying the wiring required.

公开(公告)号：DE3886203D1

公开(公告)日：1994-01-20

申请号：DE3886203

申请日：1988-04-02

Applicant: IBM

Inventor： BOCK DIETRICH DIPL ING ,  SCHULZE-SCHOELLING HERMANN DIP ,  KUMPF WOLFGANG ,  RUDOLPH PETER

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F15/177

公开(公告)号：DE2747304A1

公开(公告)日：1979-04-26

申请号：DE2747304

申请日：1977-10-21

Applicant: IBM DEUTSCHLAND

Inventor： BAZLEN DIETER DIPL ING DR ,  BERGER ROLF DIPL ING ,  BLUM ARNOLD DIPL ING ,  BOCK DIETRICH DIPL ING ,  CHILINSKI HERBERT DIPL ING ,  GENG HELLMUTH ROLAND ,  HAJDU JOHANN ,  IRRO FRITZ DIPL ING ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22 ,  G06F9/16 ,  G06F13/06

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：DE3886203T2

公开(公告)日：1994-05-19

申请号：DE3886203

申请日：1988-04-02

Applicant: IBM

Inventor： BOCK DIETRICH DIPL ING ,  SCHULZE-SCHOELLING HERMANN DIP ,  KUMPF WOLFGANG ,  RUDOLPH PETER

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F15/177

公开(公告)号：DE2756764A1

公开(公告)日：1979-06-21

申请号：DE2756764

申请日：1977-12-20

Applicant: IBM DEUTSCHLAND

Inventor： BLUM ARNOLD DIPL ING ,  BAZLEN DIETER DR ING ,  BERGER ROLF DIPL ING ,  BOCK DIETRICH DIPL ING ,  CHILINSKI HERBERT DIPL ING ,  GENG HELLMUTH ROLAND ,  GETZLAFF KLAUS ING GRAD ,  HAJDU JOHANN ,  RICHTER STEPHAN

IPC: G06F9/22 ,  G06F13/42 ,  G06F9/00 ,  G06F13/06

Abstract: The synchronising arrangement is for a processor and memory in an electronic data processing installation. There is a delay from the memory when data is demanded from it by the processor. A section of the arrangement has an output to the operations register of the processor for the provision of a code combination corresponding to a certain micro-instruction lasting for the duration of the memory delay. The operations decoder provides a corresponding output signal which stops the demand cycle counter. The operations register loads the next operation code existing at its input when it receives the next pulse of the system.