公开(公告)号：DE3886529D1

公开(公告)日：1994-02-03

申请号：DE3886529

申请日：1988-08-27

Applicant: IBM

Inventor： RUDOLPH PETER ,  BOCK DIETRICH W DIPL ING ,  SCHULZE-SCHOELLING HERMANN ING ,  MANNHERZ PETER DIPL ING

IPC: G01R31/3185 ,  G06F1/24 ,  G06F11/14 ,  G06F1/00 ,  G06F11/00

Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation (e.g.processing/logging error data) prior to a processor start. One or more reset areas are defined which are initialized /reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause (e.g. power-on) for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.

公开(公告)号：DE3853476D1

公开(公告)日：1995-05-04

申请号：DE3853476

申请日：1988-05-20

Applicant: IBM

Inventor： RUDOLPH PETER ,  BOCK DIETRICH W DIPL ING ,  SCHULZE-SCHOELLING HERMANN ING ,  GRASSMANN KURT DIPL ING

IPC: G06F11/00 ,  G06F11/07

公开(公告)号：DE3853476T2

公开(公告)日：1995-10-12

申请号：DE3853476

申请日：1988-05-20

Applicant: IBM

Inventor： RUDOLPH PETER ,  BOCK DIETRICH W DIPL ING ,  SCHULZE-SCHOELLING HERMANN ING ,  GRASSMANN KURT DIPL ING

IPC: G06F11/00 ,  G06F11/07

公开(公告)号：DE3886529T2

公开(公告)日：1994-06-30

申请号：DE3886529

申请日：1988-08-27

Applicant: IBM

Inventor： RUDOLPH PETER ,  BOCK DIETRICH W DIPL ING ,  SCHULZE-SCHOELLING HERMANN ING ,  MANNHERZ PETER DIPL ING

IPC: G01R31/3185 ,  G06F1/24 ,  G06F11/14 ,  G06F1/00 ,  G06F11/00

Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation (e.g.processing/logging error data) prior to a processor start. One or more reset areas are defined which are initialized /reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause (e.g. power-on) for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.