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公开(公告)号：DE2853546A1
公开(公告)日：1980-06-19
申请号：DE2853546
申请日：1978-12-12
Applicant: IBM DEUTSCHLAND
Inventor： BLUM ARNOLD DIPL ING , GENG HELLMUTH ROLAND ING GRAD , SCHULZE-SCHOELLING HERMANN ING , SPAETH BERND DIPL ING
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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公开(公告)号：DE2622140A1
公开(公告)日：1977-11-24
申请号：DE2622140
申请日：1976-05-19
Applicant: IBM DEUTSCHLAND
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Patent Agency Ranking
公开(公告)号：DE3886529D1
公开(公告)日：1994-02-03
申请号：DE3886529
申请日：1988-08-27
Applicant: IBM
Inventor： RUDOLPH PETER , BOCK DIETRICH W DIPL ING , SCHULZE-SCHOELLING HERMANN ING , MANNHERZ PETER DIPL ING
IPC: G01R31/3185 , G06F1/24 , G06F11/14 , G06F1/00 , G06F11/00
Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation (e.g.processing/logging error data) prior to a processor start. One or more reset areas are defined which are initialized /reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause (e.g. power-on) for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.
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公开(公告)号：DE3853476T2
公开(公告)日：1995-10-12
申请号：DE3853476
申请日：1988-05-20
Applicant: IBM
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公开(公告)号：DE3886529T2
公开(公告)日：1994-06-30
申请号：DE3886529
申请日：1988-08-27
Applicant: IBM
Inventor： RUDOLPH PETER , BOCK DIETRICH W DIPL ING , SCHULZE-SCHOELLING HERMANN ING , MANNHERZ PETER DIPL ING
IPC: G01R31/3185 , G06F1/24 , G06F11/14 , G06F1/00 , G06F11/00
Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation (e.g.processing/logging error data) prior to a processor start. One or more reset areas are defined which are initialized /reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause (e.g. power-on) for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.
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