公开(公告)号：DE3886529D1

公开(公告)日：1994-02-03

申请号：DE3886529

申请日：1988-08-27

Applicant: IBM

Inventor： RUDOLPH PETER ,  BOCK DIETRICH W DIPL ING ,  SCHULZE-SCHOELLING HERMANN ING ,  MANNHERZ PETER DIPL ING

IPC: G01R31/3185 ,  G06F1/24 ,  G06F11/14 ,  G06F1/00 ,  G06F11/00

Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation (e.g.processing/logging error data) prior to a processor start. One or more reset areas are defined which are initialized /reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause (e.g. power-on) for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.

公开(公告)号：DE69019822T2

公开(公告)日：1995-12-14

申请号：DE69019822

申请日：1990-06-27

Applicant: IBM

Inventor： SCHUMACHER NORBERT W DIPL ING ,  HOLM INGEMAR DIPL ING ,  ZILLES GERHARD D- JETTINGEN DI ,  MANNHERZ PETER DIPL ING ,  KOHLER HELMUT DIPL ING

IPC: G06F12/16 ,  G06F11/10 ,  G11C8/04

Abstract: A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.

公开(公告)号：DE69019822D1

公开(公告)日：1995-07-06

申请号：DE69019822

申请日：1990-06-27

Applicant: IBM

Inventor： SCHUMACHER NORBERT W DIPL ING ,  HOLM INGEMAR DIPL ING ,  ZILLES GERHARD D- JETTINGEN DI ,  MANNHERZ PETER DIPL ING ,  KOHLER HELMUT DIPL ING

IPC: G06F12/16 ,  G06F11/10 ,  G11C8/04

Abstract: A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.

公开(公告)号：DE3886529T2

公开(公告)日：1994-06-30

申请号：DE3886529

申请日：1988-08-27

Applicant: IBM

Inventor： RUDOLPH PETER ,  BOCK DIETRICH W DIPL ING ,  SCHULZE-SCHOELLING HERMANN ING ,  MANNHERZ PETER DIPL ING

IPC: G01R31/3185 ,  G06F1/24 ,  G06F11/14 ,  G06F1/00 ,  G06F11/00

Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation (e.g.processing/logging error data) prior to a processor start. One or more reset areas are defined which are initialized /reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause (e.g. power-on) for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.