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7 records (took 0.015 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE2755656A1

    公开(公告)日：1978-06-29

    申请号：DE2755656

    申请日：1977-12-14

    Applicant: IBM

    Inventor： BODNER RONALD EUGENE ,  CROOKS THOMAS LEE ,  KISCADEN RICHARD CRAIG

    IPC: G06F12/06 ,  G06F12/10 ,  G06F12/14 ,  G06F11/00

    Abstract: Storage protection is provided in a computer system having address translation by loading address translate registers with valid translated addresses and with special addresses. A circuit for generating a storage exception signal is connected to receive all addresses from the translate registers which are addressed by the main storage address and generates a storage exception signal in response to detecting a special address. The address translation mode is provided for both a main storage processor and a control processor with a separate address translate control register for each processor. Address translation is automatically selected based upon interrupt level. Address translation registers are also provided for I/O operations and are controlled independently from and can be in parallel with the task address translation registers.

    3.
    发明专利
    未知

    公开(公告)号：DE2530599A1

    公开(公告)日：1976-01-29

    申请号：DE2530599

    申请日：1975-07-09

    Applicant: IBM

    Inventor： BODNER RONALD EUGENE ,  CROOKS THOMAS LEE ,  GUEST JOHN EDWARD ,  ROCHESTER MINN ,  MAGRISSO ISRAEL BEN ,  SLACK KEITH KENNETH

    IPC: G06F13/12 ,  G06F13/18 ,  G06F13/28 ,  G06F9/18 ,  G06F3/00

    Abstract: Control circuitry in a computer system is responsive to an allow cycle steal signal from an I/O attachment operating in a burst or dedicated data transfer mode and generates control signals whereby the next data storage cycle is made available to an I/O device which is also capable of operating in a cycle steal mode. Upon completion of the next storage cycle, the operation reverts to burst mode and the I/O attachment operating in the burst mode is granted ensuing data storage cycles until it relinquishes a storage cycle to an I/O device capable of using and having a need for it.

    4.
    发明专利
    未知

    公开(公告)号：MX151497A

    公开(公告)日：1984-12-04

    申请号：MX18804981

    申请日：1981-06-29

    Applicant: IBM

    Inventor： BODNER RONALD EUGENE ,  CROOKS THOMAS LEE ,  WOTTRENG ANDREW HENRY

    IPC: G06F9/34 ,  G06F12/04 ,  G11C11/065

    Abstract: Storage addressing control apparatus is structured to provide either byte or word addressing of storage organized on a two byte word basis. The storage address register (6) is made shiftable whereby for byte operations it is shifted, and the bit (SAR BIT 16) shifted out of the register is used for byte selection. The contents of the storage address register are used to address storage (10) for both word and byte addressing, and no change is required. The storage access, however, for byte addressing takes place after the shift is completed and the timing is adjusted to account for the shift operation. Gate control logic is modified to facilitate the byte selection.

    6.
    发明专利
    未知

    公开(公告)号：DE2556624A1

    公开(公告)日：1976-07-08

    申请号：DE2556624

    申请日：1975-12-16

    Applicant: IBM

    Inventor： BODNER RONALD EUGENE ,  CIANCIOSI MARIO NICHOLAS ,  CROOKS THOMAS LEE ,  ROCHESTER MINN ,  MAGRISSO ISRAEL BEN ,  SLACK KEITH KENNETH ,  SMITH RICHARD STANTON

    IPC: G06F3/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/42 ,  G06F9/18

    Abstract: Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock. The CPU clock runs and the storage clock can be activated depending upon the type of I/O instruction being executed, the CPU clock runs until it reaches a second particular time state and then remains at that particular time state until the port again generates an advance time signal to the CPU. The activity taking place as the CPU clock is advancing depends upon the type of I/O instruction, but generally a data transfer occurs, and the data is entered into or transferred from local storage registers or main or control storage. The extended second particular time state is used for a de-synchronization sequence between the port and I/O attachment.

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