公开(公告)号：JP2007142417A

公开(公告)日：2007-06-07

申请号：JP2006308667

申请日：2006-11-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  BRENT A ANDERSON ,  JEFFREY B JOHNSON

IPC: H01L21/336 ,  H01L21/283 ,  H01L29/41 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a trigate field effect transistor provided with a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. SOLUTION: Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate dielectric to optimize conductivity in the channel corners. To further emphasize the electric current in the channel corners, the source/drain regions can be formed only in the upper corners of the semiconductor body. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有鳍状半导体本体的三端场效应晶体管，沟道区域和沟道区两侧的源极/漏极区域。 解决方案：厚栅极电介质层将沟道区域的顶表面和相对侧壁与栅极导体分离，以抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极电介质分离，以优化沟道角中的导电性。 为了进一步强调通道角中的电流，源极/漏极区域只能形成在半导体本体的上角处。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2012256903A

公开(公告)日：2012-12-27

申请号：JP2012163637

申请日：2012-07-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： BRENT A ANDERSON ,  BRIGHTWISH MATTHEW J ,  NORWALK EDWARD J ,  RAINIE BETHAN

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide a device which is better capable of controlling threshold voltage in FET devices.SOLUTION: Provided are a field effect transistor (FET) and a method of forming the FET, the field effect transistor comprising: a substrate 101; a SiGe layer 103 over the substrate; a semiconductor layer 105 over the SiGe layer; an insulating layer 109a adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures 111 adjacent to the insulating layer; and a second gate structure 113 over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer, an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.

Abstract translation: 要解决的问题：提供一种能够更好地控制FET器件中的阈值电压的器件。 解决方案：提供场效应晶体管（FET）和形成FET的方法，场效应晶体管包括：衬底101; 衬底上的SiGe层103; SiGe层上的半导体层105; 与基板相邻的绝缘层109a，SiGe层和半导体层; 与绝缘层相邻的一对第一栅极结构111; 以及绝缘层上的第二栅极结构113。 优选地，绝缘层与SiGe层的侧表面，半导体层的上表面，半导体层的下表面和半导体层的侧表面相邻。 优选地，SiGe层包含碳。 优选地，该对第一栅极结构基本上横向于第二栅极结构。 此外，该对第一栅极结构优选地被绝缘层封装。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2010153860A

公开(公告)日：2010-07-08

申请号：JP2009283193

申请日：2009-12-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDWARD J NOWAKU ,  BRENT A ANDERSON

IPC: H01L29/786

CPC classification number: H01L29/7841 ,  H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a body contact hybrid surface semiconductor-on-insulator (HSSOI) device formed on a semiconductor-on-insulator (SOI) substrate, and a manufacturing method thereof.
SOLUTION: A portion of a top semiconductor layer of the SOI substrate is patterned into a semiconductor fin 18 having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions 62 having a doping of a conductivity type opposite to a body region 20 of the semiconductor fin. A metal semiconductor alloy portion 82 is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region can be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects can be formed.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 解决的问题：提供一种形成在绝缘体上半导体（SOI）基板上的体接触混合表面绝缘体上半导体（HSSOI）器件及其制造方法。 解决方案：SOI衬底的顶部半导体层的一部分被图案化成具有基本垂直侧壁的半导体鳍片18。 半导体鳍片的主体区域的一部分在具有与半导体鳍片的体区域20相反的导电类型的掺杂的两个源极区域62之间的半导体鳍片的顶表面上露出。 直接在两个源极区域和两个源极区域之间的暴露体区域的顶表面上形成金属半导体合金部分82。 可以通过离子注入来增加身体区域的暴露顶部的掺杂浓度，以向身体区域提供低电阻接触，或者可以形成具有高密度结晶缺陷的复合区域。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010153787A

公开(公告)日：2010-07-08

申请号：JP2009227678

申请日：2009-09-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOWAK EDWARD J ,  BRENT A ANDERSON

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/11 ,  H01L29/786

CPC classification number: H01L21/823412

Abstract: PROBLEM TO BE SOLVED: To provide band edge controlled Vt offset devices.
SOLUTION: There are provided band edge controlled Vt offset devices, design structures for band edge controlled Vt offset devices and methods of manufacturing such structures. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a first type. The structure further includes a second FET having a channel of a second compound semiconductor of second atomic proportions resulting in a second band structure and a first type. The first compound semiconductor is different from the second compound semiconductor such that the first FET includes a first band structure different from second band structure, giving rise to a threshold voltage different from that of the second FET.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供带边缘控制的Vt偏移装置。 解决方案：提供带边缘控制的Vt偏移器件，用于带边缘控制的Vt偏移器件的设计结构以及制造这种结构的方法。 该结构包括具有第一原子比例的第一化合物半导体的通道的第一FET，其导致第一带结构和第一类型。 该结构还包括具有第二原子比例的第二化合物半导体的通道的第二FET，其导致第二带结构和第一类型。 第一化合物半导体与第二化合物半导体不同，使得第一FET包括与第二带结构不同的第一带结构，产生与第二FET不同的阈值电压。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008211214A

公开(公告)日：2008-09-11

申请号：JP2008041378

申请日：2008-02-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOWAK EDWARD J ,  BRENT A ANDERSON

IPC: H01L21/26 ,  H01L21/265 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor wafer structure which makes the interior of a wafer surface uniform in reflection factor, in order to acquire an uniform temperature change over a wafer whole region, when a rapid thermal annealing process of a semiconductor structure including a combination of different semiconductor materials is carried out. SOLUTION: In a semiconductor wafer structure in which a first device 401 includes epitaxial growth silicon germanium with a first reflection factor, and a second device 402 includes single crystal silicon with a second reflection factor, a uniform reflection factor is obtained by distributing a first device 451 as a non-functionality dummy including silicon germanium, and a second device 452 as a non-functionality dummy including single crystal silicon over the wafer whole region to obtain the same overall ratio and same density as a distribution of the first and the second device. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供使晶片内部的内部的反射系数均匀的半导体晶片结构的制造方法，为了在晶片整体区域上获得均匀的温度变化，当快速热退火 执行包括不同半导体材料的组合的半导体结构的工艺。 解决方案：在第一器件401包括具有第一反射因子的外延生长硅锗的第二器件402中，并且第二器件402包括具有第二反射系数的单晶硅的半导体晶片结构中，通过分布获得均匀的反射系数 作为包括硅锗的非功能虚拟的第一装置451和作为包括单晶硅的非功能虚拟的第二装置452在晶片整个区域上以获得与第一和第二装置451的分布相同的总比率和相同密度 第二个设备。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：GB2494564B

公开(公告)日：2018-12-19

申请号：GB201221748

申请日：2011-03-23

Applicant: IBM

Inventor： JED H RANKIN ,  MARK JAFFE ,  BRENT A ANDERSON

IPC: G06F3/041 ,  G06F3/042 ,  G06F3/044

公开(公告)号：GB2556260B

公开(公告)日：2019-09-25

申请号：GB201801219

申请日：2016-12-15

Applicant: IBM

Inventor： RAJASEKHAR VENIGALLA ,  SEONG-DONG KIM ,  BRUCE DORIS ,  BRENT A ANDERSON

IPC: H01L27/092 ,  H01L21/8238

Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

公开(公告)号：GB2556260A

公开(公告)日：2018-05-23

申请号：GB201801219

申请日：2016-12-15

Applicant: IBM

Inventor： RAJASEKHAR VENIGALLA ,  SEONG-DONG KIM ,  BRUCE DORIS ,  BRENT A ANDERSON

IPC: H01L29/786

Abstract: A method of fabricating a vertical field effect transistor including forming a first recess (170) in a substrate (100); epitaxially growing a first drain (400) from the first bottom surface (190) of the first recess (170); epitaxially growing a second drain (600) from the second bottom surface (195) of a second recess (175) formed in the substrate (100); growing a channel material (700) epitaxially on the first drain (400) and the second drain (600); forming troughs (740) in the channel material (700) to form one or more fin channels (750) on the first drain (400) and one or more fin channels (750) on the second drain (600), wherein the troughs (740) over the first drain (400) extend to the surface of the first drain (400), and the troughs (740) over the second drain (600) extend to the surface of the second drain (600); forming a gate structure (1030) on each of the one or more fin channels (750); and growing sources (1520, 1540) on each of the fin channels (750) associated with the first drain (400) and the second drain (500).