公开(公告)号：GB2595125B

公开(公告)日：2022-11-09

申请号：GB202111358

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS JEAN LOUBET

IPC: H01L29/41

Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

公开(公告)号：GB2559935B

公开(公告)日：2019-08-28

申请号：GB201809710

申请日：2016-12-09

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  EDWARD NOWAK

IPC: H01L27/088 ,  H01L21/8234

Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.

公开(公告)号：GB2562442A

公开(公告)日：2018-11-14

申请号：GB201814442

申请日：2017-01-23

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  EDWARD NOWAK ,  ALBERT MANHEE CHU

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092

Abstract: Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of C pp's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures (7) and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.

公开(公告)号：GB2595160A

公开(公告)日：2021-11-17

申请号：GB202111646

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS LOUBET

IPC: H01L21/02 ,  H01L29/786

Abstract: A technique for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. A non-planar channel region is formed having a first semiconductor layer (208), a second semiconductor layer (206), and a fin-shaped bridge layer between the first semiconductor layer (208) and the second semiconductor layer (206). Forming the non-planar channel region can include forming a nanosheet stack over a substrate (204), forming a trench (502) by removing a portion of the nanosheet stack, and forming a third semiconductor layer (602) in the trench (502). Outer surfaces of the first semiconductor layer (208), the second semiconductor layer (206), and the fin-shaped bridge region define an effective channel width of the non-planar channel region.

公开(公告)号：GB2574952A

公开(公告)日：2019-12-25

申请号：GB201913037

申请日：2018-02-06

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  EDWARD NOWAK

IPC: H01L29/786

Abstract: A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom includes a substrate (110); a vertical fin (111) on the substrate (110), wherein the vertical fin (111) has a cross-sectional area at the base (112) of the vertical fin (111) that is larger than a cross-sectional area at the top (113) of the vertical fin (111), wherein the cross-sectional area at the top (113) of the vertical fin (111) is in the range of about 10% to about 75% of the cross-sectional area at the base (112) of the vertical fin (111); and a central gated region between the base (112) and the top (113) of the vertical fin (111).

公开(公告)号：GB2595125A

公开(公告)日：2021-11-17

申请号：GB202111358

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS JEAN LOUBET

IPC: H01L29/41

Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET)architecture that includes a center fin region and one or more vertically stacked nanosheets.In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate.The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers.A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers.The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers.The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

公开(公告)号：GB2562442B

公开(公告)日：2019-05-01

申请号：GB201814442

申请日：2017-01-23

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  EDWARD NOWAK ,  ALBERT MANHEE CHU

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092

Abstract: Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of CPP's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.