公开(公告)号：JP2000069052A

公开(公告)日：2000-03-03

申请号：JP3243799

申请日：1999-02-10

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  DEBORD PIERRE ,  WIDMER ALBERT

IPC: H04J3/00 ,  H04L12/54 ,  H04L12/70 ,  H04L12/801 ,  H04L12/825 ,  H04L12/931 ,  H04L12/935 ,  H04L12/937 ,  H04L25/49 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide a flow control channel for switching architecture usable even at the time of attachment to a port expansion part. SOLUTION: Concerning the flow control method for switching architecture provided with a central switch core having a related distributed switch core access layer to communicate with a core through serial data communication links 40 and 50, the serial links 40 and 50 report coded data flows according to 8B/10B codes and prepare additional dedicated flow control channels while using two of three comma characters. In the idle or vacant state of cells, the kind of the comma character to first appear in the cell provides suitable flow control bit information.

公开(公告)号：JP2004007848A

公开(公告)日：2004-01-08

申请号：JP2003326558

申请日：2003-09-18

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  DEBORD PIERRE ,  WIDMER ALBERT

IPC: H04J3/00 ,  H04L12/54 ,  H04L12/70 ,  H04L12/801 ,  H04L12/825 ,  H04L12/931 ,  H04L12/935 ,  H04L12/937 ,  H04L25/49 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide a flow control channel for switching architecture usable even when attached to a port expansion part. SOLUTION: The flow control method for switching architecture is provided with a central switch core having a related distributed switch core access layer to communicate with a core through serial data communication links, the serial links report coded data flows according to 8B/10B codes and prepare additional dedicated flow control channels while using two of three comma characters. In the idle or vacant state of cells, the kind of the comma character to first appear in the cell provides suitable flow control bit information. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2000069004A

公开(公告)日：2000-03-03

申请号：JP3386299

申请日：1999-02-12

Applicant: IBM

Inventor： BLANC ALAIN ,  DEBORD PIERRE ,  SAUREL ALAIN ,  BREZZO BERNARD

IPC: H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/947 ,  H04Q11/04 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide a flow control mechanism for which it is not necessary to add a control lead or wiring for sending various flow control signals for decelerating the speed of several components in a switching architecture. SOLUTION: At each input port (i), an SCAL element 1000 is provided with a reception protocol interface (PINT) 511 for processing a specified protocol corresponding to an adapter, to which the input port (i) is allocated, and a first sequential means 1160 for connection through a first serial communication link 1400 with a switch core. When a cell is received by the switch core, the cell is made non-sequential by a first non-sequential means 1170. At each output port, the cell is made sequential again by a second sequential means 1190 and next sent through a second serial communication link such as coaxial cable or optical cable to a suitable SCAL.

公开(公告)号：FR2284868A1

公开(公告)日：1976-04-09

申请号：FR7431439

申请日：1974-09-11

Applicant: IBM FRANCE

Inventor： BEAUDOIN PIERRE L ,  DEBORD PIERRE

IPC: G01J1/46 ,  G01R29/24 ,  G06K7/10

Abstract: The proposed method of measuring the quantity of light received during a given time (T) by a photosensitive cell of the charge memory type involves, for each measurement operation, charging the cell to a reference level, and after an interval of time (T), measuring the loss of charge from the cell. This may be done by recharging the cell to the reference level and measuring the charging current. The above process may be applied sequentially to a group of photocells of the charge memory type.

公开(公告)号：FR2396463A1

公开(公告)日：1979-01-26

申请号：FR7720730

申请日：1977-06-30

Applicant: IBM FRANCE

Inventor： DEBORD PIERRE ,  MARIJON JEAN-LOUIS

IPC: H03M1/10 ,  H03F1/30 ,  H03F3/00 ,  H03F3/38 ,  H03M1/00 ,  H03K13/02

公开(公告)号：DE2823214A1

公开(公告)日：1979-01-04

申请号：DE2823214

申请日：1978-05-27

Applicant: IBM

Inventor： DEBORD PIERRE ,  MARIJON JEAN-LOUIS

IPC: H03M1/10 ,  H03F1/30 ,  H03F3/00 ,  H03F3/38 ,  H03M1/00 ,  G05B24/02

公开(公告)号：DE3882223T2

公开(公告)日：1994-01-27

申请号：DE3882223

申请日：1988-04-29

Applicant: IBM

Inventor： DEBORD PIERRE ,  GLAISE RENE

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H03M13/19

Abstract: A digital error detection and correction apparatus for correcting n-bit data words comprising a field of n-r data bits and a field of r error-correcting-code-ECC bits according to an error correcting code. The n-bit data words are organized in packages of b bits, and the invention is capable of correcting one package having suffered at least one hard failure and a single soft error being located in a different package. The apparatus of the invention involves an error correcting code which gives a first syndrome when the data word has suffered a first error coming from at least one error in a first package and a single error in a second package different from the first package, which also gives a second syndrôme when the data word has suffered a second error coming from at least one error in the above first package, and a single error in a third package. The error correcting code is such that the equality of the above first and second syndromes results in the equality of the first and second errors. The apparatus of the invention further includes means (24) for storing the syndrome of a first data word v, and means (24) for adding the syndrôme a second data word v min , the latter data word v min being generated from the first data word v by means of an "invert write" and an " invert read" procedure. The above addition allows the masking of the single soft error. The invention further includes means (20) for determining whether the result of the above addition provides a syndrome characterizing a single package syndrôme, in order to determine the number of the package having suffered at least one hard error, and means (21, 22, 50-XX) operative in response to said determination for directly locating the positions of the errors, either soft and hard, in order to restore the originally stored data word.

公开(公告)号：DE3882223D1

公开(公告)日：1993-08-12

申请号：DE3882223

申请日：1988-04-29

Applicant: IBM

Inventor： DEBORD PIERRE ,  GLAISE RENE

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H03M13/19

Abstract: In the digital error detection and correction appts., an error correcting code gives a first syndrome when the data word has suffered an error coming from at least one error in a first package and a single error in a second package. The second package is different from the first package, and the code gives a second syndrome when the data word has suffered a second error coming from at least one error in the first package, and a single error in a third package. The error correcting code is such that the equality of the first and second syndrome results in the equality of the first and second error. The positions of the errors are directly located and the corrected data word is restored.

公开(公告)号：DE69819129T2

公开(公告)日：2004-07-29

申请号：DE69819129

申请日：1998-10-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  DEBORD PIERRE ,  WIDMER ALBERT

IPC: H04J3/00 ,  H04L12/54 ,  H04L25/49 ,  H04L49/111 ,  H04L12/56 ,  H04Q11/04

Abstract: A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested. When the incoming flow provides data cells, the invention uses a predetermined bit within the data cell, generally that immediately following the beginning of the cell, in order to carry the flow control information.

公开(公告)号：DE69819129D1

公开(公告)日：2003-11-27

申请号：DE69819129

申请日：1998-10-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  DEBORD PIERRE ,  WIDMER ALBERT

IPC: H04J3/00 ,  H04L12/54 ,  H04L25/49 ,  H04L49/111 ,  H04L12/56 ,  H04Q11/04

Abstract: A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested. When the incoming flow provides data cells, the invention uses a predetermined bit within the data cell, generally that immediately following the beginning of the cell, in order to carry the flow control information.