Determining an optimum number of threads per core in a multi-core processor complex

    公开(公告)号:GB2605068A

    公开(公告)日:2022-09-21

    申请号:GB202207760

    申请日:2020-11-11

    Applicant: IBM

    Abstract: In a method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks, a determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.

    Dynamically switching between memory copy and memory mapping to optimize 1/O performance

    公开(公告)号:GB2602404A

    公开(公告)日:2022-06-29

    申请号:GB202203249

    申请日:2020-09-03

    Applicant: IBM

    Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.

    Dynamically switching between memory copy and memory mapping to optimize 1/O performance

    公开(公告)号:GB2602404B

    公开(公告)日:2022-11-09

    申请号:GB202203249

    申请日:2020-09-03

    Applicant: IBM

    Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.

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