公开(公告)号：GB2597634B

公开(公告)日：2022-12-21

申请号：GB202116905

申请日：2020-04-28

Applicant: IBM

Inventor： LOKESH MOHAN GUPTA ,  BETH ANN PETERSON ,  KEVIN JOHN ASH ,  KYLER ANDERSON

IPC: G06F12/0815 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/123 ,  G06F12/126

Abstract: A method for improving cache hit ratios for selected volumes when using synchronous I/O is disclosed. In one embodiment, such a method includes establishing, in cache, a first set of non-favored storage elements from non-favored storage areas. The method further establishes, in the cache, a second set of favored storage elements from favored storage areas. The method calculates a life expectancy for the non-favored storage elements to reside in the cache prior to eviction. The method further executes an eviction policy for the cache wherein the favored storage elements are maintained in the cache for longer than the life expectancy of the non-favored storage elements. A corresponding system and computer program product are also disclosed.

公开(公告)号：GB2605068A

公开(公告)日：2022-09-21

申请号：GB202207760

申请日：2020-11-11

Applicant: IBM

Inventor： BRIAN ANTHONY RINALDI ,  LOKESH MOHAN GUPTA ,  KEVIN JOHN ASH ,  MATTHEW JOSEPH KALOS ,  TRUNG NGUYEN ,  CLINT HARDY ,  LOUIS RASOR

IPC: G06F9/50

Abstract: In a method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks, a determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.

公开(公告)号：GB2579754A

公开(公告)日：2020-07-01

申请号：GB202004608

申请日：2018-08-24

Applicant: IBM

Inventor： LOKESH GUPTA ,  KEVIN JOHN ASH ,  KYLER ANDERSON ,  MATTHEW JOSEPH KALOS

IPC: G06F12/06 ,  G06F12/00

Abstract: A cache hit is generated, in response to receiving an input/output (I/O) command over a bus interface. An update for a metadata track is stored in a buffer associated with a central processing unit (CPU) that processes the I/O command, in response to generating the cache hit. The metadata track is asynchronously updated from the buffer with the stored update for the metadata track in the buffer.

公开(公告)号：GB2591424A

公开(公告)日：2021-07-28

申请号：GB202106810

申请日：2019-09-30

Applicant: IBM

Inventor： LOKESH GUPTA ,  KYLER ANDERSON ,  KEVIN JOHN ASH ,  MATTHEW BORLICK

IPC: G06F12/08

Abstract: A machine learning module receives inputs comprising attributes of a storage controller, where the attributes affect performance parameters for performing stages and destages in the storage controller. In response to an event, the machine learning module generates, via forward propagation, an output value that indicates whether to fill holes in a track of a cache by staging data to the cache prior to destage of the track. A margin of error is calculated based on comparing the generated output value to an expected output value, where the expected output value is generated from an indication of whether it is correct to fill holes in a track of the cache by staging data to the cache prior to destage of the track. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error.

公开(公告)号：GB2585320B

公开(公告)日：2021-06-09

申请号：GB202017405

申请日：2019-04-01

Applicant: IBM

Inventor： LOKESH GUPTA ,  MATTHEW BORLICK ,  KEVIN JOHN ASH

IPC: G06F12/0866 ,  G06F3/06 ,  G06F12/0895

Abstract: Provided are a computer program product, system, and method for using track locks and stride group locks to manage cache operations. A group of tracks from the storage devices are stored in a cache. Exclusive track locks for tracks in the group in the cache are granted for writes to the tracks in the group in the cache, wherein exclusive track locks can be simultaneously held for writes to different tracks in the cache. An exclusive group lock for the group of tracks in the cache is granted to destage the tracks in the group from the cache to the storage devices. The exclusive group lock is released in response to completing the destage of the tracks in the group in the cache to the storage devices.

公开(公告)号：GB2581463B

公开(公告)日：2021-01-06

申请号：GB202009753

申请日：2018-11-29

Applicant: IBM

Inventor： LOKESH MOHAN GUPTA ,  KEVIN JOHN ASH ,  CLINT HARDY ,  KARL ALLEN NEILSEN

IPC: G06F12/0868 ,  G06F3/06

Abstract: Copy source to target operations may be selectively and preemptively undertaken in advance of source destage operations. In another aspect, logic detects sequential writes including large block writes to point-in-time copy sources. In response, destage tasks on the associated point-in-time copy targets are started which include in one embodiment, stride-aligned copy source to target operations which copy unmodified data from the point-in-time copy sources to the point-in-time copy targets in alignment with the strides of the target. As a result, when write data of write operations is destaged to the point-in-time copy sources, such source destages do not need to wait for copy source to target operations since they have already been performed. In addition, the copy source to target operations may be stride-aligned with respect to the stride boundaries of the point-in-time copy targets. Other features and aspects may be realized, depending upon the particular application.

公开(公告)号：GB2584064A

公开(公告)日：2020-11-18

申请号：GB202014835

申请日：2019-02-15

Applicant: IBM

Inventor： MATTHEW BORLICK ,  LOKESH GUPTA ,  KEVIN JOHN ASH ,  KARL ALLEN NIELSEN

IPC: G06F11/10 ,  G06F3/06

Abstract: In one embodiment, virtual storage drives are allocated to RAID arrays so that no two virtual storage drives of a RAID array are mapped to the same physical storage drive. In another aspect, error handling routines are limited to virtual storage drives impacted by an error in a physical storage drive so that virtual storage drives of the physical storage drive not impacted by the error are bypassed. In yet another aspect, cache operations to a target virtual storage drive may be throttled as a function of both a limit imposed on cache operations directed to the RAID array to which the virtual storage drive is allocated, and a separate limit on cache operations directed to a group of virtual storage drives which are mapped to the same physical storage drive as the target virtual storage drive. Other features and aspects may be realized, depending upon the particular application.

公开(公告)号：GB2579329A

公开(公告)日：2020-06-17

申请号：GB202003615

申请日：2018-08-10

Applicant: IBM

Inventor： LOKESH M GUPTA ,  KEVIN JOHN ASH ,  KYLER ANDERSON

IPC: G06F12/0895 ,  G06F12/123

Abstract: A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the listof the second type of tracks.

公开(公告)号：GB2490412B

公开(公告)日：2017-12-13

申请号：GB201207226

申请日：2011-01-07

Applicant: IBM

Inventor： ROMAN PLETKA ,  EVANGELOS ELEFTHERIOU ,  ROBERT HAAS ,  XIAO-YU HU ,  YU-CHENG HSU ,  LOKESH MOHAN GUPTA ,  JOSEPH SMITH HYDE II ,  MICHAEL THOMAS BENHASE ,  ALFRED EMILIO SANCHEZ ,  KEVIN JOHN ASH

IPC: G06F12/0866

Abstract: An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests.

公开(公告)号：GB2602404A

公开(公告)日：2022-06-29

申请号：GB202203249

申请日：2020-09-03

Applicant: IBM

Inventor： LOKESH MOHAN GUPTA ,  KEVIN JOHN ASH ,  BRIAN ANTHONY RINALDI ,  KYLER ANDERSON ,  MATTHEW KALOS

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/02 ,  G06F13/42

Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.