-
公开(公告)号:GB2591424A
公开(公告)日:2021-07-28
申请号:GB202106810
申请日:2019-09-30
Applicant: IBM
Inventor: LOKESH GUPTA , KYLER ANDERSON , KEVIN JOHN ASH , MATTHEW BORLICK
IPC: G06F12/08
Abstract: A machine learning module receives inputs comprising attributes of a storage controller, where the attributes affect performance parameters for performing stages and destages in the storage controller. In response to an event, the machine learning module generates, via forward propagation, an output value that indicates whether to fill holes in a track of a cache by staging data to the cache prior to destage of the track. A margin of error is calculated based on comparing the generated output value to an expected output value, where the expected output value is generated from an indication of whether it is correct to fill holes in a track of the cache by staging data to the cache prior to destage of the track. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error.
-
公开(公告)号:GB2597634B
公开(公告)日:2022-12-21
申请号:GB202116905
申请日:2020-04-28
Applicant: IBM
Inventor: LOKESH MOHAN GUPTA , BETH ANN PETERSON , KEVIN JOHN ASH , KYLER ANDERSON
IPC: G06F12/0815 , G06F12/0868 , G06F12/0891 , G06F12/123 , G06F12/126
Abstract: A method for improving cache hit ratios for selected volumes when using synchronous I/O is disclosed. In one embodiment, such a method includes establishing, in cache, a first set of non-favored storage elements from non-favored storage areas. The method further establishes, in the cache, a second set of favored storage elements from favored storage areas. The method calculates a life expectancy for the non-favored storage elements to reside in the cache prior to eviction. The method further executes an eviction policy for the cache wherein the favored storage elements are maintained in the cache for longer than the life expectancy of the non-favored storage elements. A corresponding system and computer program product are also disclosed.
-
公开(公告)号:GB2579754A
公开(公告)日:2020-07-01
申请号:GB202004608
申请日:2018-08-24
Applicant: IBM
Inventor: LOKESH GUPTA , KEVIN JOHN ASH , KYLER ANDERSON , MATTHEW JOSEPH KALOS
Abstract: A cache hit is generated, in response to receiving an input/output (I/O) command over a bus interface. An update for a metadata track is stored in a buffer associated with a central processing unit (CPU) that processes the I/O command, in response to generating the cache hit. The metadata track is asynchronously updated from the buffer with the stored update for the metadata track in the buffer.
-
公开(公告)号:GB2605057A
公开(公告)日:2022-09-21
申请号:GB202207396
申请日:2020-11-03
Applicant: IBM
Inventor: LOKESH MOHAN GUPTA , MATTHEW BORLICK , KYLER ANDERSON , KEVIN ASH
IPC: G06F12/08
Abstract: A method for demoting data from a cache comprising heterogeneous memory types maintains, for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method removes the data element from the higher performance portion in accordance with a cache demotion algorithm. If the data element also resides in the lower performance portion and the write access count is below a first threshold, the method leaves the data element in the lower performance portion. If the data element also resides in the lower performance portion and the write access count is at or above the first threshold, the method removes the data element from the lower performance portion.
-
公开(公告)号:GB2579329A
公开(公告)日:2020-06-17
申请号:GB202003615
申请日:2018-08-10
Applicant: IBM
Inventor: LOKESH M GUPTA , KEVIN JOHN ASH , KYLER ANDERSON
IPC: G06F12/0895 , G06F12/123
Abstract: A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the listof the second type of tracks.
-
公开(公告)号:GB2602404A
公开(公告)日:2022-06-29
申请号:GB202203249
申请日:2020-09-03
Applicant: IBM
Inventor: LOKESH MOHAN GUPTA , KEVIN JOHN ASH , BRIAN ANTHONY RINALDI , KYLER ANDERSON , MATTHEW KALOS
Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.
-
公开(公告)号:GB2597634A
公开(公告)日:2022-02-02
申请号:GB202116905
申请日:2020-04-28
Applicant: IBM
Inventor: LOKESH MOHAN GUPTA , BETH ANN PETERSON , KEVIN JOHN ASH , KYLER ANDERSON
IPC: G06F12/00
Abstract: A method for improving cache hit ratios for selected volumes when using synchronous I/O is disclosed. In one embodiment, such a method includes establishing, in cache, a first set of non-favored storage elements from non-favored storage areas. The method further establishes, in the cache, a second set of favored storage elements from favored storage areas. The method calculates a life expectancy for the non-favored storage elements to reside in the cache prior to eviction. The method further executes an eviction policy for the cache wherein the favored storage elements are maintained in the cache for longer than the life expectancy of the non-favored storage elements. A corresponding system and computer program product are also disclosed.
-
公开(公告)号:GB2591424B
公开(公告)日:2021-11-10
申请号:GB202106810
申请日:2019-09-30
Applicant: IBM
Inventor: LOKESH GUPTA , KYLER ANDERSON , KEVIN JOHN ASH , MATTHEW BORLICK
Abstract: A machine learning module receives inputs comprising attributes of a storage controller, where the attributes affect performance parameters for performing stages and destages in the storage controller. In response to an event, the machine learning module generates, via forward propagation, an output value that indicates whether to fill holes in a track of a cache by staging data to the cache prior to destage of the track. A margin of error is calculated based on comparing the generated output value to an expected output value, where the expected output value is generated from an indication of whether it is correct to fill holes in a track of the cache by staging data to the cache prior to destage of the track. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error.
-
公开(公告)号:GB2578080B
公开(公告)日:2020-09-09
申请号:GB202002167
申请日:2018-07-19
Applicant: IBM
Inventor: KYLER ANDERSON , KEVIN JOHN ASH , MATTHEW JOSEPH KALOS , BETH ANN PETERSON , LOKESH MOHAN GUPTA
IPC: G06F12/0871 , G06F3/06
Abstract: Provided are a computer program product, system, and method for using a track format code in a cache control block for a track in a cache to process read and write requests to the track in the cache. A track format table associates track format codes with track format metadata. A determination is made as to whether the track format table has track format metadata matching track format metadata of a track staged into the cache. A determination is made as to whether a track format code from the track format table for the track format metadata in the track format table matches the track format metadata of the track staged. A cache control block for the track being added to the cache is generated including the determined track format code when the track format table has the matching track format metadata.
-
10.
公开(公告)号:GB2602404B
公开(公告)日:2022-11-09
申请号:GB202203249
申请日:2020-09-03
Applicant: IBM
Inventor: LOKESH MOHAN GUPTA , KEVIN JOHN ASH , BRIAN ANTHONY RINALDI , KYLER ANDERSON , MATTHEW KALOS
Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.
-
-
-
-
-
-
-
-
-