Destaging tracks with holes in storage system

    公开(公告)号:GB2591424A

    公开(公告)日:2021-07-28

    申请号:GB202106810

    申请日:2019-09-30

    Applicant: IBM

    Abstract: A machine learning module receives inputs comprising attributes of a storage controller, where the attributes affect performance parameters for performing stages and destages in the storage controller. In response to an event, the machine learning module generates, via forward propagation, an output value that indicates whether to fill holes in a track of a cache by staging data to the cache prior to destage of the track. A margin of error is calculated based on comparing the generated output value to an expected output value, where the expected output value is generated from an indication of whether it is correct to fill holes in a track of the cache by staging data to the cache prior to destage of the track. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error.

    Improving cache hit ratios for selected volumes in a storage system

    公开(公告)号:GB2597634B

    公开(公告)日:2022-12-21

    申请号:GB202116905

    申请日:2020-04-28

    Applicant: IBM

    Abstract: A method for improving cache hit ratios for selected volumes when using synchronous I/O is disclosed. In one embodiment, such a method includes establishing, in cache, a first set of non-favored storage elements from non-favored storage areas. The method further establishes, in the cache, a second set of favored storage elements from favored storage areas. The method calculates a life expectancy for the non-favored storage elements to reside in the cache prior to eviction. The method further executes an eviction policy for the cache wherein the favored storage elements are maintained in the cache for longer than the life expectancy of the non-favored storage elements. A corresponding system and computer program product are also disclosed.

    Duplicate-copy cache using heterogeneous memory types

    公开(公告)号:GB2605057A

    公开(公告)日:2022-09-21

    申请号:GB202207396

    申请日:2020-11-03

    Applicant: IBM

    Abstract: A method for demoting data from a cache comprising heterogeneous memory types maintains, for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method removes the data element from the higher performance portion in accordance with a cache demotion algorithm. If the data element also resides in the lower performance portion and the write access count is below a first threshold, the method leaves the data element in the lower performance portion. If the data element also resides in the lower performance portion and the write access count is at or above the first threshold, the method removes the data element from the lower performance portion.

    Cache management
    5.
    发明专利

    公开(公告)号:GB2579329A

    公开(公告)日:2020-06-17

    申请号:GB202003615

    申请日:2018-08-10

    Applicant: IBM

    Abstract: A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the listof the second type of tracks.

    Dynamically switching between memory copy and memory mapping to optimize 1/O performance

    公开(公告)号:GB2602404A

    公开(公告)日:2022-06-29

    申请号:GB202203249

    申请日:2020-09-03

    Applicant: IBM

    Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.

    Improving cache hit ratios for selected volumes in a storage system

    公开(公告)号:GB2597634A

    公开(公告)日:2022-02-02

    申请号:GB202116905

    申请日:2020-04-28

    Applicant: IBM

    Abstract: A method for improving cache hit ratios for selected volumes when using synchronous I/O is disclosed. In one embodiment, such a method includes establishing, in cache, a first set of non-favored storage elements from non-favored storage areas. The method further establishes, in the cache, a second set of favored storage elements from favored storage areas. The method calculates a life expectancy for the non-favored storage elements to reside in the cache prior to eviction. The method further executes an eviction policy for the cache wherein the favored storage elements are maintained in the cache for longer than the life expectancy of the non-favored storage elements. A corresponding system and computer program product are also disclosed.

    Destaging tracks with holes in storage system

    公开(公告)号:GB2591424B

    公开(公告)日:2021-11-10

    申请号:GB202106810

    申请日:2019-09-30

    Applicant: IBM

    Abstract: A machine learning module receives inputs comprising attributes of a storage controller, where the attributes affect performance parameters for performing stages and destages in the storage controller. In response to an event, the machine learning module generates, via forward propagation, an output value that indicates whether to fill holes in a track of a cache by staging data to the cache prior to destage of the track. A margin of error is calculated based on comparing the generated output value to an expected output value, where the expected output value is generated from an indication of whether it is correct to fill holes in a track of the cache by staging data to the cache prior to destage of the track. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error.

    Dynamically switching between memory copy and memory mapping to optimize 1/O performance

    公开(公告)号:GB2602404B

    公开(公告)日:2022-11-09

    申请号:GB202203249

    申请日:2020-09-03

    Applicant: IBM

    Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.

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