公开(公告)号：JPH1092169A

公开(公告)日：1998-04-10

申请号：JP18130297

申请日：1997-07-07

Applicant: IBM

Inventor： BRIAN J CONNOLLY ,  MARK W KELLOGG ,  BRUCE G HEEZERUZETSUTO

IPC: G11C5/00 ,  G06F13/16 ,  G06F13/40 ,  G11C11/401 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To minimize a data line load by providing a bus switch between a system and a RAM and then comprising a logic circuit to produce a signal for enabling this switch into an ASIC. SOLUTION: DRAM chips 301 to 304 and DRAM chips 311 to 314 are connected to a bus switch 309, while DRAM chips 305 to 308 and DRAM chips 315 to 318 are connected to a bus switch 319. A couple of bus switches are connected to ASIC 310 which is connected to a RAS pin and a CAS pin. A data bus load can be minimized by forming a bank DIMM 30 or DIMM 40 by utilizing bus switches 309, 319 or bus switches 409, 419.

公开(公告)号：GB2611729B

公开(公告)日：2025-04-02

申请号：GB202301413

申请日：2021-06-01

Applicant: IBM

Inventor： BRIAN J CONNOLLY ,  KYU-HYOUN KIM

IPC: G06F21/79 ,  G06F1/3225 ,  G06F12/14 ,  G11C5/14

Abstract: A memory system for storing data that includes providing a memory module having one or more memory devices and a voltage regulator for controlling voltage levels supplied to the one or more memory devices, wherein the voltage regulator has a first state that permits write and read operations with the one or more memory devices, and a second state where the voltage regulator prevents at least read operations with the one or more memory devices the system configured to store an encryption key in ROM on the voltage regulator; copy the encryption key value from the ROM to a voltage regulator register; set a voltage regulator encryption timer for a period of time; and transition the voltage regulator to the second state in response to the voltage regulator encryption timer expiring.